Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-/spl mu/m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm/sup 2/.

A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex We pro pose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC The prototype 12b 50 MS/s ADC achieves an ENOB of 104b at Nyquist, and a figure-of-merit of 52 f J/conversion-step The ADC achieves low-power, high-resolution and high-speed operation without calibration The ADC is fabricated in 65 nm and 90 nm CMOS and occupies a core area of only 016 mm2

A SAR-Assisted Two-Stage Pipeline ADC

A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 078 LSB, an INL of 17 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 12 V supply

A 12-Bit 200-MHz CMOS ADC

A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-/spl mu/m dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm/sup 2/.

A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC

A low-power 14-b 100-MS/s analog-to-digital converter (ADC) is described. The prototype ADC achieves low-power consumption and small die area by sharing an opamp between two successive pipeline stages. Further reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique. The ADC, implemented in a 0.18-mum dual-gate-oxide (DGO) CMOS technology, achieves 72.4-dB signal-to-noise and distortion ratio, 88.5-dB spurious free dynamic range, and 11.7 effective number of bits at full sampling rate with a 46-MHz input while consuming 230-mW from a 3-V supply.

A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC

The prototype ADC is implemented in 0.18mum dual gate-oxide (DGO) CMOS technology and achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input while consuming 230mW from a 3V supply. Recently, power saving has been achieved by removing the explicit active S/H. Instead of removing the S/H, this work solves these drawbacks by merging the active S/H amplifier with the first MDAC (SMDAC). Thus, the ADC achieves low-power operation without sacrificing speed or accuracy.

A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC

A 10 b 80 MHz pipelined ADC with an active area of 1.85 mm/sup 2/ is realized in a 0.18 /spl mu/m dual gate oxidation CMOS process and achieves 72.8 dBc SFDR, 57.92 dB SNR, and 9.29 ENOB for a 100 MHz input at full sampling rate. The ADC shares an amplifier between two successive pipeline stages in order to achieve a power consumption of 69 mW at 3 V.

A 69 mW 10 b 80 MS/s pipelined CMOS ADC

A first stage circuit for a high-speed, high-resolution pipeline analog-to-digital converter (ADC) implements operational amplifier (opamp) sharing and capacitor sharing to combine the sample-and-hold (SAH) and the MDAC (multiplying digital to analog converter) functions in the first residue stage of the pipeline ADC. In one embodiment, the first stage circuit includes a sampling capacitor, an amplifier, a feedback capacitor array and a comparator. The sampling capacitor and the feedback capacitor array are configured by switches to operate in a sampling/MDAC mode, a discharge mode and a hold mode. In this manner, the sample-and-hold operation and the MDAC operation are merged into the first stage circuit of the pipeline ADC to achieve low power and high speed of operation.

Byung-Moo Min

Papers

A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC

A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC

A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC

A 69 mW 10 b 80 MS/s pipelined CMOS ADC

Opamp and capacitor sharing scheme for low-power pipeline ADC