A surface creep model is presented for analyzing Cu-to-Cu direct bonding under thermal compression. The driving force is a pressure gradient, which squeezes layers of atoms to fill voids at the bonding interface. The link among the key parameters of surface roughness, experimental bonding time, temperature, and pressure is presented in a kinetic equation. The theoretical bonding time can be calculated through these key parameters. The benchmark of the theoretical bonding time is the time required for the bonding area to reach 95%, which is measured from TEM images of the bonding interface. The experimental bonding time might be longer, and the bonding area might larger than 95%. Because the bonding mechanism includes surface diffusion and grain boundary diffusion, it is difficult to distinguish their individual influence. Therefore, the effective diffusivity ( D e f f ) is calculated from the bonding conditions of other research and the equation of bonding model. If the bonding surface is highly (111)-oriented, the D e f f is close to the (111) surface diffusivity. From the surface creep bonding model, the theoretical bonding time of grain boundary diffusion is very sensitive to the bonding temperature, while that of (111) surface diffusion is not. Additionally, at low temperature bonding (

A kinetic model of copper-to-copper direct bonding under thermal compression

This article focuses on the 3-D modeling methodology development of the wafer-to-wafer hybrid bonding (W2W-HB) annealing process. With its successful application in a 2-stack wafer-to-wafer bonding, the Cu-to-Cu bonding area is derived and compared for various design and process conditions, such as dishing value, annealing temperature, and dwell duration, through-silicon via (TSV) depth, and TSV/Cu pad pitch. Cu protrusion during the annealing process induces peeling stresses on both Cu and dielectric bonding interfaces. The resulting debonding risk for both Cu and dielectric bonding is assessed by comparing the peak interfacial peeling stresses for various scenarios. The impact of wafer designs with or without TSV has also been studied. The key advantage of this numerical study is to help establish design and process guidelines to shorten the W2W-HB process development cycle and achieve robust bonding integrity. The outcome of this work has been successfully implemented in the actual process.

Wafer-to-Wafer Hybrid Bonding Development by Advanced Finite Element Modeling for 3-D IC Packages

Cu/oxide Hybrid Bonding (HB) technology is currently the ultimate fine pitch 3D interconnect solution to reach submicron pitches. It's an attractive technique to address the needs of several applications such as smart imagers, high-performance computing and memory-on-logic folding. But test and characterization of such fine-grained 3D interconnect is still an open issue; Cu-Cu interconnects are prone to many structural defects due to fabrication process, such as misalignment, which needs to be thoroughly tested to ensure the performance of 3D-ICs. In this work, we focus on testing and characterizing, on-wafer, misalignment defect induced at the bonding step. A misalignment test structure was fabricated in a Wafer-to-Wafer (W2W) assembly configuration with a pitch of 3.42µm and 1.44µm using a very small measurement step for an accurate misalignment measurement (respectively 45nm and 22nm). Electrical tests have been performed using five multi-pitch wafers with 71 measurements points per wafer. The experimental results show that the results of the proposed test structure are aligned with conventional overlay measurements. Finally, the impact of misalignment defect on resistance and capacitance parameters was demonstrated.

Characterization of Fine Pitch Hybrid Bonding Pads using Electrical Misalignment Test Vehicle

We adopted (111)-oriented Cu with high surface diffusivity to achieve low-temperature and low-pressure Cu/SiO2 hybrid bonding. Electroplating was employed to fabricate arrays of Cu vias with 78% (111) surface grains. The bonding temperature can be lowered to 200 °C, and the pressure is as low as 1.06 MPa. The bonding process can be accomplished by a 12-inch wafer-to-wafer scheme. The measured specific contact resistance is 1.2 × 10−9 Ω·cm2, which is the lowest value reported in related literature for Cu-Cu joints bonded below 300 °C. The joints possess excellent thermal stability up to 375 °C. The bonding mechanism is also presented to provide more understanding on hybrid bonding.

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Low-Temperature Cu/SiO2 Hybrid Bonding with Low Contact Resistance Using (111)-Oriented Cu Surfaces

We have developed the novel fabrication process that has realized the robust ultra-fine pitch, 1 μm pitch, wafer level face-to-face Cu-Cu hybrid bonding. For the stable electrical connection between upper Cu pads and lower Cu pads, wet process, ECD process and CMP process were examined to protrude Cu connection pads steadily and we have verified that our advanced process integration has achieved high electrical yields. Moreover, the 1.4μm pitch level Cu-Cu hybrid bonding has been successfully introduced into face-to-back bonding interface. We have developed the novel wafer thinning process to minimize total thickness variation (TTV) of Si and roundness of wafer edge, at the same time.

Development of face-to-face and face-to-back ultra-fine pitch Cu-Cu hybrid bonding

Hybrid bonding is a high-density technology for 3D integration but further interconnect scaling down could jeopardize electrical and reliability performance. A study of the influence of hybrid bonding pitch shrinkage on a 3D stacked backside illuminated CMOS image sensor was performed from a process, device performance and robustness perspectives, from $8.8\ \mu\mathrm{m}$ down to $1.44\ \mu \mathrm{m}$ bonding pitches. As a result no defect related to smaller bonding pads was evidenced neither by thermal cycling nor by electromigration, thus validating fine-pitch hybrid bonding robustness and introduction for next generation image sensors.

C. Charles

Papers

Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness