Deposits of clastic carbonate-dominated (calciclastic) sedimentary slope systems in the rock record have been identified mostly as linearly-consistent carbonate apron deposits, even though most ancient clastic carbonate slope deposits fit the submarine fan systems better. Calciclastic submarine fans are consequently rarely described and are poorly understood. Subsequently, very little is known especially in mud-dominated calciclastic submarine fan systems. Presented in this study are a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) that reveals a >250 m thick calciturbidite complex deposited in a calciclastic submarine fan setting. Seven facies are recognised from core and thin section characterisation and are grouped into three carbonate turbidite sequences. They include: 1) Calciturbidites, comprising mostly of highto low-density, wavy-laminated bioclast-rich facies; 2) low-density densite mudstones which are characterised by planar laminated and unlaminated muddominated facies; and 3) Calcidebrites which are muddy or hyper-concentrated debrisflow deposits occurring as poorly-sorted, chaotic, mud-supported floatstones. These

Phd by thesis

Time evolution of self-heating and current filamentation are discussed in this paper for shallow-trench-isolation (STI)-type drained-enhanced n-channel metal-oxide-semiconductor (DeNMOS) devices. A deeper insight toward regenerative n-p-n action and its impact over various phases of filamentation and the final thermal runaway is presented. A modified STI-type DeNMOS device is proposed in order to achieve an improvement (~2×) in the failure threshold (IT2) and electrostatic discharge (ESD) window (VT2). The performance and filament behavior of the standard device under charge-device-model-like ESD conditions is also presented, which is further compared with the proposed modified device.

Part II: On the Three-Dimensional Filamentation and Failure Modeling of STI Type DeNMOS Device Under Various ESD Conditions

We present experimental and simulation studies of shallow trench isolation (STI)-type drain-extended n-channel metal-oxide-semiconductor devices under human body model (HBM)-like electrostatic discharge (ESD) conditions. Physical insight toward pulse-to-pulse instability is given. Both the current (ITLP) and time evolution of various events such as junction breakdown, parasitic bipolar triggering, and the base push-out effect are discussed in detail. Differences between the 2-D and 3-D simulation (modeling) approaches are presented, and the importance of 3-D technology-computer-aided-design-based modeling is discussed. Furthermore, a deeper physical insight toward the base push-out is given, which shows significant power dissipation due of space charge build-up, which is found at the onset of self-heating in the 2-D plane.

Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in $R_{\mathrm{{\scriptscriptstyle ON}}}$ and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

A robust FinFET silicon-controlled rectifier (SCR) LDMOS ESD protection device is developed. Replacing the drain contact implant to the P+ implant from N+ implant creates an SCR inside the LDMOS and when the N+ contact is removed a Schottky SCR LDMOS is created. The ESD performance of the baseline FinFET LDMOS is Zero, while that of the SCR LDMOS is 9.2 mA/ $\mu {\mathrm{ m}}$ and Schottky SCR is 4.6 mA/ $\mu \text{m}$ respectively.

Engineering ESD Robust LDMOS SCR Devices in FinFET Technology

Second breakdown phenomenon in advanced NMOS ESD protection devices has remained an enigma due to the complex electrical and thermal effects that are responsible for its triggering. For the first time, we present a critical study of the high current phenomenon in ultra short-time scale to understand the physics of instability in protection devices around the second breakdown region. It is demonstrated that for advanced protection devices, carrier heating in the high field drain region causes a fall in the saturation drift velocity, which increases the transit time of carriers through the depletion region. This in turn, causes greater impact ionization due to higher accumulation of avalanche-generated carriers; leading to the formation of a propagating ionizing wave front, which culminates in a regenerative avalanche injection induced second breakdown failure

New physical insight and modeling of second breakdown (It/sub 2/) phenomenon in advanced esd protection devices

Second breakdown phenomenon (It2) in drain extended NMOS (DENMOS) which is associated with complex triggering of the parasitic BJT is relatively less understood. We present experiments and models to understand the physics of snapback in DENMOS in nanometer scale technologies. Avalanche injection phenomenon at the drain contact has been analyzed for a 90 nm DENMOS transistor under high current stressing

An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies

We present for the first time, analysis of irreversible snapback caused due to the regenerative n-p-n turn-on in a DENMOS through a critical understanding of 'thermal runaway' under ESD conditions. The estimated It2 value from transient simulations has been correlated with the quasi-steady TLP data. A new regenerative bipolar turn-on induced failure model has been proposed and corroborated with experimental observations and failure analysis. We have also investigated the current crowding mechanism to understand the improvement in It2 value under gate and substrate biasing.

C. Duwury

Papers

New physical insight and modeling of second breakdown (It/sub 2/) phenomenon in advanced esd protection devices

An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies

A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism under ESD Conditions