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Proceedings ArticleDOI

A Microscopic Understanding of Nanometer Scale DENMOS Failure Mechanism under ESD Conditions

TL;DR: In this paper, an analysis of irreversible snapback caused due to the regenerative n-p-n turn-on in a DENMOS through a critical understanding of "thermal runaway" under ESD conditions is presented.
Abstract: We present for the first time, analysis of irreversible snapback caused due to the regenerative n-p-n turn-on in a DENMOS through a critical understanding of 'thermal runaway' under ESD conditions. The estimated It2 value from transient simulations has been correlated with the quasi-steady TLP data. A new regenerative bipolar turn-on induced failure model has been proposed and corroborated with experimental observations and failure analysis. We have also investigated the current crowding mechanism to understand the improvement in It2 value under gate and substrate biasing.
Citations
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Journal ArticleDOI
TL;DR: In this paper, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies, and the tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations.
Abstract: In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in $R_{\mathrm{{\scriptscriptstyle ON}}}$ and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

23 citations


Cites background from "A Microscopic Understanding of Nano..."

  • ...As shown, there is an early formation of space charge within the device, which leads to quasi-saturation effects in the device characteristics and various device reliability issues [20]–[22]....

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Journal ArticleDOI
TL;DR: In this paper, the off-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic discharge (ESD) devices for high-voltage applications in standard lowvoltage complementary MOS technology is studied.
Abstract: The OFF-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an n+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both OFF-state and ESD reliability.

14 citations

Proceedings ArticleDOI
15 Apr 2012
TL;DR: In this article, the improvement in ESD performance of HV DENMOS and LDMOS obtained by using selective drain extension silicide blocking (SBLK) was demonstrated through 3D TCAD and TLP measurements.
Abstract: This paper demonstrates the dramatic improvement in ESD performance of HV DENMOS and LDMOS obtained by using selective drain extension silicide blocking (SBLK). The results are validated through 3D TCAD and TLP measurements on different technologies. Measured D.C. Id-Vd characteristics show minimal performance impact due to the addition of SBLK region.

13 citations


Cites background from "A Microscopic Understanding of Nano..."

  • ...INTRODUCTION ESD protection for high voltage applications has proven to be challenging due to the poor performance of high voltage components under high-current conditions [1]....

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Proceedings ArticleDOI
01 Jun 2014
TL;DR: In this article, the authors demonstrate that isolated DEMOS devices are also vulnerable to failures induced by the parasitic NPN to isolation due to insufficient body resistance and demonstrate the effectiveness of using selectively SBLKed drain fingers to enable self protection.
Abstract: DEMOS devices have poor ESD robustness due to kirk effect induced snapback. Isolated DEMOS devices, in addition to the kirk effect induced second snapback, are also vulnerable to failures induced by the parasitic NPN to isolation. In addition, we demonstrate here, that some DEMOS devices show intrinsically non-scalable breakdown current (IT1) behavior due to insufficient body resistance. We then demonstrate techniques to restore IT1 scalability in these devices. We finally demonstrate the effectiveness of using selectively SBLKed drain fingers to enable self protection in small DEMOS devices.

9 citations


Cites background from "A Microscopic Understanding of Nano..."

  • ...DEMOS devices are well known to have poor drain-to-source ESD current handling capability due to kirk-effect induced voltage snapback [1, 2]....

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Proceedings ArticleDOI
01 Sep 2018
TL;DR: In this article, the physical insights of Drain Extended FinFET under ESD stress condition are explored, and key features like bipolar triggering, conductivity modulation and localized hot spot formation pertaining to DeFinFET failure mechanism are discussed comprehensively.
Abstract: In this paper, physical insights of Drain extended FinFET under ESD stress condition is explored. Key features like bipolar triggering, conductivity modulation and localized hot spot formation pertaining to DeFinFET failure mechanism are discussed comprehensively. Non-uniformity and filament formation in multi-finger DeFinFET is explored.

3 citations


Cites background from "A Microscopic Understanding of Nano..."

  • ...Several works have been reported, discussing the failure mechanism in De-MOS devices [4, 5], and the space charge modulation, a physical phenomenon was considered as the key role in forming non-uniformities in the current conduction [6,7]....

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References
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Journal ArticleDOI
TL;DR: In this paper, it was shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.
Abstract: A rapid type of second breakdown observed in silicon n+-p-n-n+transistors is shown to be due to avalanche injection at the collector n-n+junction. Localized thermal effects, which are usually associated With second breakdown, are shown to play a minor role in the initiation of the transition to the low voltage state. A useful tool in the analysis of avalanche injection is the n+-n-n+diode, which exhibits negative resistance at a critical voltage and current. A close correspondence between the behavior of the diode and the transistor (open base) is established both theoretically and experimentally. Qualitative agreement with the proposed model is obtained for both directions of base current flow. It is shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.

214 citations

Journal ArticleDOI
TL;DR: In this paper, a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors is presented, and its implications for the design of ESD protection for deep-submicron CMOS technologies are analyzed.
Abstract: This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width (W) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current (I/sub t2i/) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.

49 citations

Journal ArticleDOI
TL;DR: In this article, the authors studied the influence of termination layout of the source field on the hot-spot dynamics and discussed conditions for filament motion under non-destructive snap-back conditions, which help homogenize the time averaged current density distribution and enhance the device robustness against electrostatic discharges.
Abstract: Integrated vertical DMOS transistors of a 90-V smart power technology are studied under short-duration current pulses. Movement of current filaments and multiple hot spots observed by transient interferometric mapping under nondestructive snap-back conditions are reported. Device simulations show that the base push-out region associated with the filament can move from cell to cell along the drain buried layer due to the decrease of the avalanche generation rates by increasing temperature. The influence of the termination layout of the source field on the hot-spot dynamics is studied. Conditions for filament motion are discussed. The described mechanisms help homogenizing the time averaged current-density distribution and enhance the device robustness against electrostatic discharges.

46 citations

Journal ArticleDOI
TL;DR: In this article, two different protection diodes are investigated with electrothermal simulation and transient interferometric thermal mapping experiments in a new complementary approach, and the prediction capability of the simulation tool is validated up to the thermal failure of the p-n junction.
Abstract: Two different protection diodes are investigated with electrothermal simulation and transient interferometric thermal-mapping experiments in a new complementary approach. The prediction capability of the simulation tool is validated up to the thermal failure of the p-n junction. The temperature distribution and its dynamics during the application of high-current pulses are studied by comparing the calculated and experimental optical phase shifts: a quantitative agreement both in temporal evolution and space distribution of temperature is obtained up to 1100 K.

12 citations

01 Jan 2005
TL;DR: In this article, two different protection diodes are investigated with electrothermal simulation and transient interferometric thermal-mapping experiments in a new complementary approach, and the prediction capability of the simulation tool is validated up to the thermal failure of the p-n junction.
Abstract: Two different protection diodes are investigated with electrothermal simulation and transient interferometric thermal-mapping experiments in a new complementary approach. The prediction capability of the simulation tool is validated up to the thermal failure of the p-n junction. The temperature distri- bution and its dynamics during the application of high-current pulses are studied by comparing the calculated and experimental optical phase shifts: a quantitative agreement both in temporal evolution and space distribution of temperature is obtained up to 1100 K.

9 citations