Molecular scale charge motion in disordered organic materials at ambient temperature occurs via a hopping-type mechanism with rates dictated both by the charge transfer integral and by the reorganization energy due to geometric relaxation This contribution presents a systematic theoretical analysis of cation internal reorganization energies for a broad family of organic oligoheterocycles-variation of reorganization energy with oligomer chain length, heteroatom identity, and a range of heterocycle substituents provides key information on important structural properties governing internal reorganization energies At room temperature, the range in reorganization energies induced by substituent variations corresponds to a >10(2)-fold variation in intrinsic hole transfer rate, suggesting that changes in reorganization energy dominate variations in charge-transfer rates for many semiconducting/conducting oligomers

Hopping transport in conductive heterocyclic oligomers: reorganization energies and substituent effects.

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

Dielectric breakdown mechanisms in gate oxides

In this paper a review of the more "fundamental" concerns regarding the scaling of the gate dielectric in the ultrathin regime is presented. Material issues are discussed pertaining to the integration of silicon oxynitride and oxide/nitride stacked layers and how such films might reduce or minimize boron penetration problems and address leakage current and reliability concerns. A methodology is presented to calculate device and chip lifetimes for MOS structures on the basis of data extracted from voltage- and temperature-accelerated measurements. Some integration issues regarding higher-k materials are also discussed because of their ability to solve the scaling problem. However, difficulties are involved in integrating them into a CMOS process flow.

Scaling the gate dielectric: materials, integration, and reliability

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

Total ionizing dose radiation effects on the electrical properties of metal-oxide-semiconductor devices and integrated circuits are complex in nature and have changed much during decades of device evolution. These effects are caused by radiation-induced charge buildup in oxide and interfacial regions. This paper presents an overview of these radiation-induced effects, their dependencies, and the many different approaches to their mitigation.

Radiation effects and hardening of MOS technology: devices and circuits

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V/sub d/, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V/sub d/'s, along the stress time axis, until the characteristics merge into a single curve.

A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFETs

The authors present observations of changes in the gate capacitances of a MOSFET as a result of hot-carrier stressing and propose capacitance measurement as a method for evaluation of trapped charge. The effect of hot-carrier stressing on 2- mu m effective channel length n-channel MOSFETs was monitored by measuring the gate-to-source capacitance and the gate-to drain capacitance. It was found that after electrically stressing a junction of the transistor, capacitances associated with the stressed junction were reduced, whereas the capacitances of the unstressed junction were found to have increased. The observation is explained in terms of the change in channel potential near the stressed junction due to negative trapped charge. >

Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement

Hot carrier degradation in n-channel MOSFET's is studied using gate capacitance and charge pumping current for three gate stress voltages: V/sub g//spl sim/V/sub b/, V/sub d//2, V/sub d/. The application of these two sensitive techniques reveals new information on the types of trap charges and the modes of degradation. At low V/sub g/ stress near threshold voltage, the fixed charge is attributed to holes. For high V/sub g/ stress, the fixed charge is predominantly electrons. Data for mid V/sub g/ stress suggest little net fixed charge trapping. Interface traps are observed for all stress conditions and are demonstrated from differential gate capacitance spectra to exhibit both donor and acceptor trap behavior. Mid V/sub g/ stress is shown to result in the highest density of interface traps. These traps can be annealed to a large extent for temperatures up to 300/spl deg/C. A post-stress generation of interface traps is observed at low V/sub g/ stress, in agreement with recent observation. Further, a linear relation is found to exist between the change in overlap gate capacitance and the increase in peak charge pumping current, and suggests spatial uniformity in the degradation of the interface. >

A study of hot carrier degradation in NMOSEET's by gate capacitance and charge pumping current

Experimental data are presented on the effects of varying deposition parameters of SiH4/NH3 gas flow ratio, rf power, deposition pressure and substrate temperature, on the deposition rate, refractive index, hydrogen content and etch rates of PECVD silicon nitride films. BHF etch rate in these films are generally high and this is shown to be associated with the high hydrogen content. N-H and Si-H bond concentrations are measured in the range 1-4×1022 cm-3. The substrate temperature dependence of the etch rate exhibits a maximum for films deposited at 150°C. The behaviour is attributed to the incorporation of both hydrogen and oxygen, the effects on the etch rate of which are suggested to act in opposing directions.

https://iopscience.iop.org/article/10.1143/JJAP.25.1490/pdf

Silicon Nitride Films Prepared by Plasma-Enhanced Chemical Vapour Deposition (PECVD) of SiH 4 /NH 3 /N 2 Mixtures: Some Physical Properties

Yttrium oxide Y2O3 films are prepared by rf sputtering on to silicon substrates and characterized by current‐voltage I‐V, capacitance‐voltage C‐V and capacitance‐time C‐t measurements. Relative permittivity increases with substrate heating from room temperature to 600 °C. As‐deposited films show large flat‐band voltage and interface trap density, which improve upon annealing in oxygen or hydrogen ambient up to 600 °C. However, film resistivity degrades by about 1 order of magnitude. Large hysteresis is observed in the C‐V curves, particularly for films deposited at high substrate temperature. This observation is attributed to the interfacial polarization at the Y2O3/SiO2 (native) interface. By monitoring the device capacitance over time for a given applied voltage, the resultant curves can be fitted to an exponential time dependent relation: C(t)=α0−α1exp(−t/τ). The time constant is further found to exhibit a dependence on the applied voltage of the form τ=τ0exp(−V0/V). Comparison with electron‐beam deposited films is also made.

C.H. Ling

Papers

A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFETs

Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement

A study of hot carrier degradation in NMOSEET's by gate capacitance and charge pumping current

Silicon Nitride Films Prepared by Plasma-Enhanced Chemical Vapour Deposition (PECVD) of SiH 4 /NH 3 /N 2 Mixtures: Some Physical Properties

Study of rf‐sputtered yttrium oxide films on silicon by capacitance measurements