This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

Full On-Chip CMOS Low-Dropout Voltage Regulator

This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

/pdf/a-transient-enhanced-low-quiescent-current-low-dropout-119enznkif.pdf

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor. The proposed voltage-spike detection circuit is applied to an output-capacitorless LDO implemented in a standard 0.35-?m CMOS technology (where VTHN ? 0.5 V and VTHP ? -0.65 V). Experimental results show that the LDO consumes 19 ?A only. It regulates the output at 0.8 V from a 1-V supply, with dropout voltage of 200 mV at the maximum output current of 66.7 mA. The voltage spike and the recovery time of the LDO with the proposed voltage-spike detection circuit are reduced to about 70 mV and 3 ?s, respectively, whereas they are more than 420 mV and 30 ?s for the LDO without the proposed detection circuit.

An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection

A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm2. The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV VDO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario.

/pdf/a-high-slew-rate-push-pull-output-amplifier-for-low-vw851eqr5j.pdf

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHN ap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current.

/pdf/a-low-dropout-regulator-for-soc-with-q-reduction-4to3aikqi9.pdf

A Low-Dropout Regulator for SoC With $Q$ -Reduction

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-/spl mu/m CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time.

A frequency compensation scheme for LDO voltage regulators

In the frequency compensation scheme of low drop out (LDO) voltage regulators, a zero generated by the series combination of load capacitor and its electro static resistance (ESR) plays an important role. This frequency compensation tends to be inefficient, as one has to take into consideration a range of specified values for load capacitor and R/sub ESR/, along with their variation with process and temperature. This paper presents a robust frequency compensation scheme that generates a zero internally without relying on RESR of load capacitor. The proposed frequency compensation has better RF noise rejection, low power consumption and improved transient response. The LDO regulator is designed in 0.35/spl mu/m TSMC technology.

A robust frequency compensation scheme for LDO regulators

A switched-current oscillator having a dc current source adapted to charge a capacitor so that the capacitor charging time is controlled based on a sequence of (pseudo)randomly selected values, each of those values defining a corresponding charging time. A discharge device is adapted to discharge the capacitor if the voltage across the capacitor reaches a threshold voltage, at which point the next value in the sequence is selected to determine the next charging time. A square-wave clock signal having spread-spectrum characteristics is generated in the oscillator by using the series of charge-discharge cycles corresponding to the sequence of randomly selected values to toggle a flip-flop operating as a delay line and zero-order hold.

C.K. Chava

Papers

A frequency compensation scheme for LDO voltage regulators

A robust frequency compensation scheme for LDO regulators

Switched-current oscillator for clock-frequency spreading