Strained-semiconductor-on-insulator device structures

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer

CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION

A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs

Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits

The first n-SiGe-channel MOSFETs fabricated using high-dose germanium implantation and solid-phase epitaxy are reported The polysilicon-gate MOSFETs were fabricated in the same chip in which conventional polysilicon-gate n-MOSFETs were made and their electrical characteristics are compared The SiGe-channel MOSFETs show some significantly better electrical characteristics as compared to the silicon-channel MOSFETs For example, the SiGe MOSFETs show higher drain conductance in the triode region and higher transconductance overall The threshold voltage of the SiGe MOSFET appears to be smaller and the carrier mobility in the channel appears to be higher >

SiGe-channel n-MOSFET by germanium implantation

Silicon-germanium devices including MOSFETs, photogates and photodiodes, are produced by implanting the Si or polycrystalline silicon substrate with Ge + , to realize active SiGe regions within Si which are substantially free from defects, at an appropriate point in the fabrication by conventional techniques.

Method for making silicon-germanium devices using germanium implantation

This paper presents a detailed comparison of the measured and computed electrical characteristics of polysilicon emitter bi-polar transistors over a wide range of processing conditions. Detailed electrical measurements are made of both the emitter resistance and the base and collector current as a function of base-emitter voltage. Devices with arsenic- and phosphorus-doped emitters are considered, as well as both with and without a deliberately grown interfacial oxide layer. The theoretical characteristics are computed using a unified model that incorporates both transport and tunneling mechanisms. It is shown that the measured emitter resistances across a wide range of processing conditions can be satisfactorily explained using a tunneling model with a single value for the electron effective barrier height (0.4 eV). Values for the modeling parameters are obtained, in some cases uniquely by measurement, and in others by fitting the experimental results. In devices with a deliberately grown interfacial oxide, the base current is suppressed to such an extent that recombination in the single-crystal emitter and in the base becomes important.

Comparison of experimental and computed results on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors

A new charge control relation, the general transient charge control (GTCC) relation, is developed and shown to be a natural extension to conventional charge control theory by correctly accounting for the partitioning of stored charge within semiconductor devices. Although the transient integral charge control (TICC) relation was originally thought to represent such an extension, it is shown that the TICC relation neglects the influence of recombination on the displacement components of the non-quasi-static (NQS) currents, and is therefore only a special case of the GTCC relation. From the GTCC relation, a physically based weighting function emerges which is shown to be the optimum weighting function with which to weight the continuity equation in the generalized partitioned-charge-based (PCB) modeling methodology. An extended TICC relation that is valid for transparent emitters with widely varying emitter surface recombination velocities is developed. Also, a new charge control relation for the emitter is developed which yields a semianalytic expression, involving the static minority-carrier charge distribution, for calculating the optimum charge partitioning in arbitrarily doped emitters. The TICC, the extended TICC, and the GTCC relations are compared with accurate AC numerical calculations of charge partitioning in a wide variety of Gaussian emitter profiles. >

http://ieeexplore.ieee.org/iel1/16/2677/00081640.pdf

The general transient charge control relation: a new charge control relation for semiconductor devices

We computationally study the effect of uniaxial strain in modulating the spontaneous emission of photons in silicon nanowires. Our main finding is that a one to two orders of magnitude change in spontaneous emission time occurs due to two distinct mechanisms: (A) Change in wave function symmetry, where within the direct bandgap regime, strain changes the symmetry of wave functions, which in turn leads to a large change of optical dipole matrix element. (B) Direct to indirect bandgap transition which makes the spontaneous photon emission to be of a slow second order process mediated by phonons. This feature uniquely occurs in silicon nanowires while in bulk silicon there is no change of optical properties under any reasonable amount of strain. These results promise new applications of silicon nanowires as optoelectronic devices including a mechanism for lasing. Our results are verifiable using existing experimental techniques of applying strain to nanowires.

/pdf/reversible-modulation-of-spontaneous-emission-by-strain-in-xsn1smn3ua.pdf

C.R. Selvakumar

Papers

SiGe-channel n-MOSFET by germanium implantation

Method for making silicon-germanium devices using germanium implantation

Comparison of experimental and computed results on arsenic- and phosphorus-doped polysilicon emitter bipolar transistors

The general transient charge control relation: a new charge control relation for semiconductor devices

Reversible Modulation of Spontaneous Emission by Strain in Silicon Nanowires