An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The contributions of nonlocal mechanisms to nonlinear transport in semiconductors, with special emphasis on hot‐electron emission at heterojunctions and its variations which are now commonly termed real‐space transfer effects, are reviewed. The goal is to equitably account for and bring together the body of literature that has developed, often independently, in the U.S. and the former Soviet Union as well as in Europe and Japan.

Nonlocal and nonlinear transport in semiconductors: Real-space transfer effects

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 /spl mu/m to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si/sub 3/N/sub 4/ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6/spl times/10/sup 6/ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns. >

Advanced TFT SRAM cell technology using a phase-shift lithography

The charge injection transistor, or CHINT, is a three-terminal semiconductor device based on controlled real-space transfer of hot electrons between two conducting layers separated by a potential barrier. The symmetry of hot-electron injection by real-space transfer with respect to the polarity of the heating field allows the implementation of novel circuit elements. Thus, in the basic CHINT structure, the collector current is an exclusive OR function of voltages applied to the emitter electrodes. Moreover, the authors have proposed and demonstrated a multiterminal device structure with three symmetric logic inputs that performs both the NOR and the AND logic functions, and can be switched between these functions in the course of the circuit operation. Symmetry properties of real-space transfer transistors have been studied theoretically, with the help of continuation modeling and transient device simulation. These studies reveal a variety of instabilities and a striking novelty of multiply connected current-voltage characteristics. The authors have found that the CHINT can support anomalous steady states in which hot-electron injection occurs in the absence of any voltage between the emitter electrodes. In these states, some of which are not only stationary but also stable with respect to small perturbations, the electron heating is due to the fringing field from the collector electrode. Some of the anomalous states break the reflection symmetry in the plane normal to the channel at midpoint. The study elucidates the formation of hot-electron domains.

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Symmetry of the real-space transfer and collector-controlled states in charge injection transistors

A method for producing a thin-film transistor by using a crystalline silicon film that has been formed by using nickel as a metal element for accelerating crystallization of silicon. In forming source and drain regions, phosphorus as an element for gettering nickel is introduced therein by ion implantation. Nickel gettering is effected by annealing. For example, in the case of producing a P-channel thin-film transistor, both phosphorus and boron are used. Boron determines a conductivity type, and phosphorus is used as a gettering material.

Method of using phosphorous to getter crystallization catalyst in a p-type device

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L/sub ch/. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L/sub ch/, L/sub LDD/, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of approximately 1.25 mu A at 5 V and a leakage current of approximately 0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is approximately 7*10/sup 6/. >

Inverted thin-film transistors with a simple self-aligned lightly doped drain structure

In a graded InAlGaAs superlattice grown by molecular-beam epitaxy at 500 {degree}C, we have observed a novel steady-state photovoltaic effect which arises from an internal polarization field under above-band-gap ({ital h}{nu}{gt}{ital E}{sub {ital g}}) illumination. The saturation value is {similar to}0.1 V and the response time to the illumination is limited by the oscilloscope resolution to {similar to}2 ns. The observations are in quantitative agreement with a theoretical model by which we fit our data and extract a minority-carrier lifetime {tau}{sub {ital e}} of {similar to}30 ps. This effect is substantially reduced in a second wafer grown at 550 {degree}C, in which {tau}{sub {ital e}} is expected to be long.

Steady-state photovoltaic effect in asymmetrical graded superlattices

The authors report a study of the hot-electron real space transfer (RST) between two InGaAs layers separated by a 200-nm InAlAs barrier. The electron heating is generated by an electric field applied parallel to one of the layers, which represents a two-dimensional hot-electron emitter. Strong suppression of the RST by an increased concentration n/sub s/ of the emitter electrons was observed. With increasing n/sub s/, the critical heating voltage, required to initiate the RST, increases. At a fixed heating voltage, a sudden quench of the RST is observed as n/sub s/ increases. Both phenomena are explained by an electronic screening effect which smooths out the nonuniformity of the electric field in the emitter channel. >

C.-T. Liu

Papers

Inverted thin-film transistors with a simple self-aligned lightly doped drain structure

Steady-state photovoltaic effect in asymmetrical graded superlattices

Quench of hot-electron real space transfer by electronic screening