Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures

We report that crystalline phases with ferroelectric behavior can be formed in thin films of SiO2 doped hafnium oxide. Films with a thickness of 10 nm and with less than 4 mol. % of SiO2 crystallize in a monoclinic/tetragonal phase mixture. We observed that the formation of the monoclinic phase is inhibited if crystallization occurs under mechanical encapsulation and an orthorhombic phase is obtained. This phase shows a distinct piezoelectric response, while polarization measurements exhibit a remanent polarization above 10 μC/cm2 at a coercive field of 1 MV/cm, suggesting that this phase is ferroelectric. Ferroelectric hafnium oxide is ideally suited for ferroelectric field effect transistors and capacitors due to its excellent compatibility to silicon technology.

Ferroelectricity in hafnium oxide thin films

A number of recent efforts have attempted to design accelerators for popular machine learning algorithms, such as those involving convolutional and deep neural networks (CNNs and DNNs). These algorithms typically involve a large number of multiply-accumulate (dot-product) operations. A recent project, DaDianNao, adopts a near data processing approach, where a specialized neural functional unit performs all the digital arithmetic operations and receives input weights from adjacent eDRAM banks.This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner. While the use of crossbar memory as an analog dot-product engine is well known, no prior work has designed or characterized a full-fledged accelerator based on crossbars. In particular, our work makes the following contributions: (i) We design a pipelined architecture, with some crossbars dedicated for each neural network layer, and eDRAM buffers that aggregate data between pipeline stages. (ii) We define new data encoding techniques that are amenable to analog computations and that can reduce the high overheads of analog-to-digital conversion (ADC). (iii) We define the many supporting digital components required in an analog CNN accelerator and carry out a design space exploration to identify the best balance of memristor storage/compute, ADCs, and eDRAM storage on a chip. On a suite of CNN and DNN workloads, the proposed ISAAC architecture yields improvements of 14.8×, 5.5×, and 7.5× in throughput, energy, and computational density (respectively), relative to the state-of-the-art DaDianNao architecture.

ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars

A memristor is a resistive device with an inherent memory. The theoretical concept of a memristor was connected to physically measured devices in 2008 and since then there has been rapid progress in the development of such devices, leading to a series of recent demonstrations of memristor-based neuromorphic hardware systems. Here, we evaluate the state of the art in memristor-based electronics and explore where the future of the field lies. We highlight three areas of potential technological impact: on-chip memory and storage, biologically inspired computing and general-purpose in-memory computing. We analyse the challenges, and possible solutions, associated with scaling the systems up for practical applications, and consider the benefits of scaling the devices down in terms of geometry and also in terms of obtaining fundamental control of the atomic-level dynamics. Finally, we discuss the ways we believe biology will continue to provide guiding principles for device innovation and system optimization in the field. This Perspective evaluates the state of the art in memristor-based electronics and explores the future development of such devices in on-chip memory, biologically inspired computing and general-purpose in-memory computing.

The future of electronics based on memristive systems

On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

Complementary resistive switches for passive nanocrossbar memories

We demonstrate the fabrication of a 3D memory architecture based on the resistive switching effect. Resistive memory (RRAM) is under wide investigation since it is non-volatile, promises fast operation and can be integrated into high density architectures like crossbar arrays. Here, silver-doped methyl-silsesquioxane (MSQ) is integrated in crossbar array structures for the following reasons. First, the material at the same time provides good planarization properties so that emerging lithography techniques like nanoimprint lithography (NIL) are applicable. Second, we could prove that silver-doped MSQ can be used as resistive switching material on the nano scale. Using this technique, crossbar arrays with a minimum feature size of only 100 nm are stacked on each other and the functionality is proved by electrical characterization. This comprises the doubling of the memory density and furthermore even higher integration is in principle not limited by this technique, while the CMOS overhead increases only slightly.

High density 3D memory architecture based on the resistive switching effect

Recently, the sneak-path obstacle in passive crossbar arrays has been overcome by the invention of complementary resistive switches (CRSs) consisting of two bipolar antiserially connected memristive elements. Here, we demonstrate the vertical integration of CRS cells based on Cu/SiO2/Pt bipolar resistive switches. CRS cells were fabricated and electrically characterized, showing high resistance ratios (Roff/Ron >; 1500) and fast switching speed (<; 120 μs). The results are one step further toward the realization of high-density passive nanocrossbar-array-based gigabit memory devices.

Integrated Complementary Resistive Switches for Passive High-Density Nanocrossbar Arrays

The ultimate sensitivity of any solid state device is limited by fluctuations. Fluctuations are manifestations of the thermal motion of matter and the discreteness of its structure which are also inherent ingredients during the resistive switching process of resistance random access memory (RRAM) devices. In quest for the role of fluctuations in different memory states and to develop resistive switching based nonvolatile memory devices, here we present our study on random telegraph noise (RTN) resistance fluctuations in Cu doped Ge0.3Se0.7 based RRAM cells. The influence of temperature and electric field on the RTN fluctuations is studied on different resistance states of the memory cells to reveal the dynamics of the underlying fluctuators. Our analysis indicates that the observed fluctuations could arise from thermally activated transpositions of Cu ions inside ionic or redox “double-site traps” triggering fluctuations in the current transport through a filamentary conducting path. Giant RTN fluctuation...

/pdf/probing-cu-doped-ge0-3se0-7-based-resistance-switching-nel3mu4v06.pdf

Probing Cu doped Ge0.3Se0.7 based resistance switching memory devices with random telegraph noise

Memristive switches are promising devices for future nonvolatile nanocrossbar memory devices. In particular, complementary resistive switches (CRSs) are the key enabler for passive crossbar array implementation solving the sneak path obstacle. To provide logic along with memory functionality, “material implication” (IMP) was suggested as the basic logic operation for bipolar resistive switches. Here, we show that every bipolar resistive switch as well as CRSs can be considered as an elementary IMP logic unit and can systematically be understood in terms of finite-state machines, i.e., either a Moore or a Mealy machine. We prove our assumptions by measurements, which make the IMP capability evident. Local fusion of logic and memory functions in crossbar arrays becomes feasible for CRS arrays, particularly for the suggested stacked topology, which offers even more common Boolean logic operations such as and and nor .

Carsten Kügeler

Papers

Complementary resistive switches for passive nanocrossbar memories

High density 3D memory architecture based on the resistive switching effect

Integrated Complementary Resistive Switches for Passive High-Density Nanocrossbar Arrays

Probing Cu doped Ge0.3Se0.7 based resistance switching memory devices with random telegraph noise

Crossbar Logic Using Bipolar and Complementary Resistive Switches