Showing papers by "Chandra Mouli published in 2008"

Floating Body Field-Effect Transistors, and Methods of Forming Floating Body Field-Effect Transistors

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1_X)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1_X)-comprising region and the gate dielectric. The semiconductor SixGe(1_X)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Semiconductor constructions, electronic systems, and methods of forming cross-point memory arrays

Abstract: The present application concerns vertical stacks of memory units (14, 16, 18), with individual memory units each having a memory element (28), a wordline (22), a bitline (24) and at least one diode (26). The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks- of memory unit cells, with individual unit cells containing cross-point memory and at least one diode, and adjacent memory units being spaced from one another by a passivation material (20).

Selectively Conducting Devices, Diode Constructions, Constructions, and Diode Forming Methods

Abstract: Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods.

Semiconductor devices and electronic systems comprising floating gate transistors and methods of forming the same

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Low power memory device with JFET device structures

Abstract: There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory cells having a memory element and a JFET access device electrically coupled to the memory element. The memory cells may be isolated using diffusion based isolation.

Semiconductor structures including a movable switching element, systems including same and methods of forming same

Abstract: Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a conductive contact are disclosed. Upon application of a threshold voltage, the movable switching element may deform toward the conductive contact via an electrical field, establishing electrical contact between the conductive pad and the conductive contact. Various methods may be used to form such semiconductor structures, and switching devices including such semiconductor structures. Memory devices and electronic systems include such switching devices.

Jfet device structures and methods for fabricating the same

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

Semiconductor device structures including transistors with energy barriers adjacent to transistor channels and associated methods

Abstract: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.

Semiconductor structures including a movable switching element and systems including same

Abstract: Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a conductive contact are disclosed. Upon application of a threshold voltage, the movable switching element may deform toward the conductive contact via an electrical field, establishing electrical contact between the conductive pad and the conductive contact. Various methods may be used to form such semiconductor structures, and switching devices including such semiconductor structures. Memory devices and electronic systems include such switching devices.

Derivation of threshold voltage and drain current for cylindrical MOSFET and application to a recessed MOSFET

Abstract: Threshold voltage and drive current for a cylindrical MOSFET have been rigorously derived for the first time. An approximate expression for these quantities is presented for the purpose of analytical calculations. The model has been verified against TCAD simulations. The characteristics of a recessed gate MOSFET is analysed using these models.

Stacked non-volatile memory with silicon carbide-based amorphous silicon finFETs

Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

Capacitor-less floating-body volatile memory cell comprising a pass transistor and a vertical read/write enable transistor and manufacturing and programming methods thereof

Abstract: A capacitor-less floating-body memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell (82) in a active area of a substantially physically isolated portion of the bulk semiconductor substrate (10). A pass transistor (70) is formed on the active area for coupling with a word line (88). The capacitor-less memory cell further includes a read/write enable transistor (76) vertically configurated along at least one vertical side of the active area, sharing a floating source/drain region (80) with the pass transistor, and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

JFET devices with PIN gate stacks

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

JFET Devices with PIN Gate Stacks and Methods of Making the Same

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Memory devices, transistor devices and related methods

Abstract: A memory device and method of making the memory device. The memory device comprises a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

Time-Resolved Programming Current Measurement and Modeling for nand -type Nanodot Flash Cell

Abstract: The programming/erasing transient behavior of the NAND-type nanodot flash cell has been studied for the first time. By using an equivalent circuit model, the transient current through each layer in the dielectric stack can be monitored during the pulse programming/erasing. It is found that the oxide charging current leads the tunneling current during programming, and the charge built up at the storage node causes the gradual leakage current increase in the blocking dielectric. Parameters such as the current ratio of the tunnel oxide and the blocking layer and the programming efficiency of the nanodot cell can be calculated. The simulation result has been verified by the time-resolved current measurement.