Showing papers by "Chandra Mouli published in 2015"

An anti-ferroelectric gated Landau transistor to achieve sub-60 mV/dec switching at low voltage and high speed

Abstract: Landau field effect transistors promise to lower the power-dissipation of integrated circuits (ICs) by reducing the subthreshold swing (S) below the Boltzmann limit of 60 mV/dec. The key idea is to replace the classical gate insulator with dielectrics that exhibit negative capacitance (NC) associated with double-well energy landscape, for example, ferroelectrics (FE), air-gap capacitors, or a combination thereof. Indeed, S is dramatically reduced, constrained only by the limits of hysteresis-free operation. Unfortunately, the following limitations apply (i) the need for capacitance matching constrains steep S only to the small subthreshold region for FE based negative capacitance field effect transistor (NCFET) and requires an insulator too thick for sub-20 nm scaling; (ii) the kinetics of mechanical switching for airgap based NCFET obviate high-speed operation; and (iii) the lattice mismatch between the substrate and the dielectric makes defect-free integration difficult. In this article, we demonstrate ...

Field effect transistor constructions and methods of programming field effect transistors to one of at least three different programmed states

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

Semiconductor isolation structure and method of manufacture

Abstract: A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.

Selectively conducting devices, diode constructions, methods of forming diodes and methods of current modulation

Abstract: Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second electrodes. The dielectric material may be configured to conduct current from the first electrode to the second electrode when a first voltage is applied across the first electrode and the second electrode. Furthermore, the dielectric material may be configured to inhibit current from flowing from the second electrode to the first electrode when a second voltage having a polarity opposite that of a polarity of the first voltage is applied across the first electrode and the second electrode. The diode material may comprise a plurality of layers of different dielectric materials arranged in order of increasing barrier height. Quantum wells may form at junctions of layers of the plurality responsive to the first voltage. Some embodiments include diode forming methods.

Semiconductor Constructions, and Methods of Forming Cross-Point Memory Arrays

Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.