Chen-Yong Cher

TL;DR: A multi-petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, allows for a maximum packaging density of processing nodes from an interconnect point of view.

TL;DR: This paper uses simulation and emulation results to understand the accuracy tradeoffs associated with a variety of high-level error injection techniques and explains the causes of high degrees of inaccuracies associated witherror injection techniques at higher levels of abstraction.

TL;DR: This paper outlines a new architecture, the Active Memory Cube, which reduces the energy of computation significantly by performing computation in the memory module, rather than moving data through large memory hierarchies to the processor core.

TL;DR: This paper investigates the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions.

TL;DR: In this article, a monitoring and control system integrated into a microprocessor system includes a hierarchical architecture having a plurality of layers, each layer in the hierarchy is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher level to control and manage power usage in the microprocessor systems both globally and locally.