Arpith C. Jacob

TL;DR: This paper outlines a new architecture, the Active Memory Cube, which reduces the energy of computation significantly by performing computation in the memory module, rather than moving data through large memory hierarchies to the processor core.

TL;DR: The architecture of the portions of the application that are accelerated in the FPGA are described, and the integration of these FPGa-accelerated portions with the existing BLASTP software is described.

TL;DR: This paper describes a combination of programming language features, compiler techniques, operating system interfaces, and hardware design that can effectively hide memory latency for the processing lanes in an AMC system and shows how this approach improves the performance of a set of representative benchmarks important in high performance computing applications.

TL;DR: In this paper, an apparatus and method for performing similarity searching on a data stream with respect to a query string are disclosed, where the data stream comprises a plurality of data substrings, and where the query string comprises of query substrings.

TL;DR: Experiments with three benchmarks suggest that emerging hardware technologies can significantly boost performance of a wide range of applications by increasing compute cycles and bandwidth and reducing latency.