This paper presents a high-efficiency 60-GHz on-off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip commu- nication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is de- rived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation tech- nique, resulting in a 30-dB on-off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of 0.077 mm . A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit. Index Terms—Bulk driven, CMOS, drive amplifier (DA), low power, millimeter wave, modulator, neutralization, on-off keying (OOK), transmitter (TX), voltage-controlled oscillator (VCO), wireless network-on-chip (WiNoC).

A 1.2-pJ/bit 16-Gb/s 60-GHz OOK Transmitter in 65-nm CMOS for Wireless Network-On-Chip

This paper presents for the first time the design, fabrication, and demonstration of a micromachined silicon dielectric waveguide based sub-THz interconnect channel for a high-efficiency, low-cost sub-THz interconnect, aiming to solve the long-standing intrachip/interchip interconnect problem. Careful studies of the loss mechanisms in the proposed sub-THz interconnect channel are carried out to optimize the design. Both theoretical and experimental results are provided with good agreement. To guide the channel design, a new figure of merit is also defined. The insertion loss of this first prototype with a 6-mm-long interconnect channel is about 8.4 dB at 209.7 GHz, with a 3-dB bandwidth of 12.6 GHz.

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High-Efficiency Micromachined Sub-THz Channels for Low-Cost Interconnect for Planar Integrated Circuits

Traditional TEM-based I/O communication through either PCB traces or free space has significant path loss and electromagnetic (EM) interferences that are hardly employed toward low-power and dense I/Os for data server. We propose a 0.1–1 THz or sub-terahertz (THz) I/O interface using surface plasmonic polariton (SPP) interconnects in CMOS to obtain high-energy efficiency and low-crosstalk interconnect. The surface wave can be established with on-chip generation and further deployed for signal propagation by corrugating periodical grooves onto the traditional transmission line. It will result in a strongly localized electromagnetically wave onto the surface of top-layer metal in wideband, leading to the broadband low EM coupling between many core and memories. Moreover, we have also developed a high on/off ratio split-ring-resonator-based modulator to support the sub-THz I/O communication. The proposed SPP interconnect achieves data rate of 25 Gb/s with 0.016 pJ/b/mm energy efficiency at 140 GHz in 65-nm CMOS. In addition, two surface-wave channels placed with 2.4- $\mu \text{m}$ spacing exhibits an average −28-dB crosstalk ratio.

An Energy-Efficient and Low-Crosstalk Sub-THz I/O by Surface Plasmonic Polariton Interconnect in CMOS

This paper presents for the first time the design, fabrication, and demonstration of a dielectric waveguide (DWG)-based ortho-mode sub-THz interconnect channel for planar chip-to-chip communications. By combining the proposed new transition of microstrip line with DWG orthogonally, the ortho-mode transition is constructed to form an ortho-mode channel. The measured minimum insertion losses for the $E_{y11}$ mode and the $E_{x11}$ mode are 6.6 dB with 20.3-GHz 3-dB bandwidth and 6.5 dB with 55.2-GHz 3-dB bandwidth, respectively. The simulation and measurement results agree well with each other.

Ortho-Mode Sub-THz Interconnect Channel for Planar Chip-to-Chip Communications

This paper presents a novel dielectric waveguide based G-band interconnect. By using a new transition of microstrip line to dielectric waveguide, the interconnect achieves low insertion loss and wide bandwidth. The measured minimum insertion loss is 4.9 dB with 9.7 GHz 1-dB bandwidth. Besides, the structure is based on standard micromachined processing and easy to integrate with conventional packaging.

Low-loss and Broadband G-Band Dielectric Interconnect for Chip-to-Chip Communication

A 5Gbps bi-directional RF-Interconnect (RF-I) with multi-drop and arbitration capabilities is designed and realized in 65nm CMOS. The baseband data are modulated in RF-I by using a 60GHz carrier in ASK format. An on-chip differential transmission line (TL) is used as the communication channel, which minimizes the latency (9ps/mm) only under the speed-of-light limitation. We insert λ/4 directional couplers for implementing multi-drops without signal reflection. We also use MOS switches along the signal path to reconfigure/arbitrate communication priority for multi-drops. This design consists of four TX/RX drops along a 5.5mm TL ring, supports destructive reading with fixed priority, and can reconfigure any drop as the transmitter. The tested data rate of the RF-I is 5Gbps with lower than 10−12 BER. The average power consumptions for the link are 1.33pJ/b and 0.24pJ/b/mm.

Chewpu Jou

Papers

A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration