A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

Recent progress in ultra-low-power circuit design is creating new opportunities for cubic millimeter computing. Robust low-voltage operation has reduced active mode power consumption considerably, but standby mode power consumption has received relatively little attention from low-voltage designers. In this work, we describe a low-voltage processor called the Phoenix Processor that has been designed at the device, circuit, and architecture levels to minimize standby power. A test chip has been implemented in a carefully selected 0.18 μm process in an area of only 915 x 915 μm 2 . Measurements show that Phoenix consumes 35.4 pW in standby mode and 226 nW in active mode.

A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode

Recent progress in ultra-low-power circuit design is creating new opportunities for cubic millimeter computing. Robust low-voltage operation has reduced active mode power consumption considerably, but standby mode power consumption has received relatively little attention from low-voltage designers. In this work, we describe a low-voltage processor called the Phoenix Processor that has been designed at the device, circuit, and architecture levels to minimize standby power. A test chip has been implemented in a carefully selected 0.18 mum process in an area of only 915 times 915 mum2. Measurements show that Phoenix consumes 35.4 pW in standby mode and 226 nW in active mode.

A variable feedback impedance is presented capable of providing high linearity (e.g. as represented by IP 2 and IP 3 ) and high linear range (e.g. as represented by P 1 dB) when used in a feedback path of an RF amplifier in the presence of high voltage amplitudes.

Amplifier with variable feedback impedance

A low noise 5-GHz differential Colpitts CMOS voltage-controlled oscillator (VCO) is proposed in this letter. The Colpitts VCO core adopts only PMOS in a 0.18-/spl mu/m CMOS technology to achieve a better phase noise performance since PMOS has lower 1/f noise than NMOS. The VCO operates from 4.61 to 5 GHz with 8.3% tuning range. The measured phase noise at 1-MHz offset is -120.42 dBc/Hz at 5 GHz and -120.99 dBc/Hz at 4.61 GHz. The power consumption of the VCO core is only 3 mW. To the authors' knowledge, this differential Colpitts CMOS VCO achieves the best figure of merit (FOM) of 189.6 dB at 5-GHz band.

A 5-GHz low phase noise differential colpitts CMOS VCO

A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations. In addition, the divider of a SIPLL [3-5] cannot be powered down to save the power as in [1, 2]. In this paper, a divider-less SIPLL with self-adjusted injection timing is presented.

A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing

In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.

60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS

A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal.

Cmos millimeter-wave variable-gain low-noise amplifier

A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.

Low-noise amplifier with gain enhancement

This paper describes a leading-edge 0.18 /spl mu/m CMOS logic foundry technology. Very aggressive design rules and borderless contacts render a 4.4 /spl mu/m/sup 2/ embedded (synchronous cache) 6T SRAM cell demonstrated in a 1 Mb vehicle with very high yield. Robust dual-gate oxides were developed to support 1.5-2 V core logic as well as 3.3 V periphery (I/O) circuitry. Advanced modular core device technology using 32 /spl Aring/ oxides for 1.8-2 V operation and 27 /spl Aring/ oxides for 1.5-1.7 V applications support competitive high-performance (MPU/graphics) or low-standby power (mobile) applications. Transient-enhanced diffusion is effectively used in I/O devices to enhance hot-carrier lifetime. This is the first 0.18 /spl mu/m technology demonstrating a highly manufacturable 6 to 7 level low-k (HSQ)/AlCu interconnect system with tightest metal pitch (0.46 /spl mu/m M1 and 0.56 /spl mu/m at intermediate levels), as well as aggressive borderless and fully stacked vias without poisoning problems. AlCu/FSG and dual-damascene Cu/oxide interconnect options have also been proven with comparable SRAM yield to the AlCu/HSQ system.

Hsieh-Hung Hsieh

Papers

A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing

60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS

Cmos millimeter-wave variable-gain low-noise amplifier

Low-noise amplifier with gain enhancement

A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications