Chia-Ping Hsieh

TL;DR: Four dies that contain two insulated gate bipolar transistors and two diodes in this study were embedded and integrated in a carrier substrate to produce a next-generation power inverter module, suggesting better power switching performance.

TL;DR: In this article, a pre-molding technology is used to achieve extra-thin chip thickness down to 10µm, where the top layer of the outermost microjoint has the most serious reliability concern under a load of temperature change.

TL;DR: In this article, phase masks of sub-micron period, centimeter long, with the zero-order intensity suppressed down to 8% were generated by using interferometric lithography along with the Taguchi method as an optimization tool for processing phase masks.

TL;DR: In this paper, the thermal mismatch stresses with regard to interconnects composed through silicon via (TSV) and microbump induced by thermal cycling loads is considered and parametric estimations of the induced stress/strain from the geometries of fine-pitch TSVs under temperature cycling loads are also performed by using a nonlinear finite element analysis.

TL;DR: In this article, a finite element-based simulation method to predict the EM/ thermomigration (TM)/ stressmigration (SM) physical reliability and experimental validation is proposed, which considers other physical behaviors including stress and temperature effects for future applications such as stretchable and foldable electric products.