Showing papers by "Chih-Kong Ken Yang published in 1999"
TL;DR: In this article, a serial link transmitter fabricated in a large-scale integrated 0.4/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects.
Abstract: A serial link transmitter fabricated in a large-scale integrated 0.4-/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5/spl times/2.0 mm/sup 2/ of die area.
166 citations
17 Jun 1999
TL;DR: A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-/spl mu/m CMOS process to investigate the design of an equalized multi-level link.
Abstract: A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-/spl mu/m CMOS process to investigate the design of an equalized multi-level link. Clocked differential amplifiers were used to sample the input, followed by high-speed comparators with current-summed offset cancellation. Input bandwidth was measured at 2.5 GHz. Eight 1.5-GSample/sec flash A/D converters were interleaved to achieve the aggregate sample rate.
79 citations
17 Jun 1999
TL;DR: An 8-Gb/s 0.3/spl mu/m CMOS transceiver uses 4-PAM and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel low-pass effects as discussed by the authors.
Abstract: An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit pre-shaping in combination with receive equalization to reduce ISI due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear PLL with a loop bandwidth >30 MHz, phase margin >48/spl deg/ and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8-Gbps data is successfully detected by the receiver after a 10-m coaxial cable. The 2 mm/spl times/2 mm chip consumes 1.1 W at 8 Gbps with a 3-V supply.
72 citations
TL;DR: A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described, which achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12.5%.
Abstract: A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-/spl mu/m CMOS technology and operates from a single 2.5-V supply.
50 citations