Journal ArticleDOI
A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter
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TLDR
In this article, a serial link transmitter fabricated in a large-scale integrated 0.4/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects.Abstract:
A serial link transmitter fabricated in a large-scale integrated 0.4-/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the process-limited on-chip frequency, the transmitter output driver is designed as a 5:1 multiplexer to reduce the required clock frequency to one-fifth the symbol rate, or 1 GHz. At 5 Gsym/s (10 Gbis), a data eye opening with a height >350 mV and a width >100 ps is achieved at the source. After 10 m of a copper coaxial cable (PE142LL), the eye opening is reduced to 200 mV and 90 ps with pre-emphasis, and to zero without filtering, The chip dissipates 1 W with a 3.3-V supply and occupies 1.5/spl times/2.0 mm/sup 2/ of die area.read more
Citations
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Journal ArticleDOI
Jitter and phase noise in ring oscillators
TL;DR: A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented in this paper, where the impulse sensitivity functions are used to derive expressions for the jitter.
Journal ArticleDOI
RF/wireless interconnect for inter- and intra-chip communications
TL;DR: This paper introduces a novel RF/wireless interconnect concept for future inter- and intra-ULSI communications, based on low loss and dispersion-free microwave signal transmission, near-field capacitive coupling, and modem multiple-access algorithms.
Patent
Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
Alistair D. Black,Kurt Chan +1 more
TL;DR: In this article, a switch, switched architecture and process for transferring data through an FCAL switch is disclosed, which uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch.
Journal ArticleDOI
Low-power area-efficient high-speed I/O circuit techniques
TL;DR: A 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/ of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS technology is presented.
Book ChapterDOI
The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
References
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Journal Article
The design of CMOS radio-frequency integrated circuits, 2nd edition
TL;DR: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Book
The Design of CMOS Radio-Frequency Integrated Circuits
TL;DR: In this article, the authors present an expanded and thoroughly revised edition of Tom Lee's acclaimed guide to the design of gigahertz RF integrated circuits, which is packed with physical insights and design tips, and includes a historical overview of the field in context.
Journal ArticleDOI
Jitter and phase noise in ring oscillators
TL;DR: A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented in this paper, where the impulse sensitivity functions are used to derive expressions for the jitter.
Journal ArticleDOI
Transmitter equalization for 4-Gbps signaling
William J. Dally,John W. Poulton +1 more
TL;DR: 0.5-micron CMOS transmitter and receiver circuits that use active equalization to overcome the frequency-dependent attenuation of copper lines are developed.