Showing papers by "Christian Landrault published in 2007"

DERRIC: A Tool for Unified Logic Diagnosis

Abstract: This paper presents DERRIC (Diagnosis of logic ERRors in VLSI Integrated Circuits), a diagnostic tool targeting most of the fault models used in practice today. This tool is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The underlying method of DERRIC is based on the Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) that consists in identifying critical lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each critical line, so that root causes of failures can be finally determined. The main advantage of this method is that it does not need to explicitly consider each fault model during the diagnosis process. Experiments on ISCAS'85 and ITC'99 benchmarks show the efficiency of the proposed tool in terms of diagnosis resolution.

Slow write driver faults in 65nm SRAM technology: analysis and March test solution

Abstract: This paper presents an analysis of the electrical origins of slow write driver faults (SWDFs) (van de Goor et al., 2004) that may affect SRAM write drivers in 65nm technology. This type of fault is the consequence of resistive-open defects in the control part of the write driver. It involves an erroneous write operation when the same write driver performs two successive write operations with opposite data values. In the first part of the paper, we present the SWDF electrical phenomena and their consequences on the SRAM functioning. Next, we show how SWDFs can be sensitized and observed and how a standard March test is able to detect this type of fault

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Abstract: Scan technology increases the switching activity well beyond that of the functional operation of an IC In this paper, we first discuss the issues of excessive peak power during scan testing and highlight the importance of reducing peak power particularly during the test cycle (ie between launch and capture) so as to avoid noise phenomena such as IR-drop or Ground Bounce Next, we propose a scan cell reordering solution to minimize peak power during all test cycles of a scan testing process The problem of scan cell reordering is formulated as a constrained global optimization problem and is solved by using a simulated annealing algorithm Experimental evidence and practical implications of the proposed solution are given at the end of the paper For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during TC up to 51% compared to an ordering provided by an industrial synthesis tool Fault coverage and test time are left unchanged by the proposed solution

Fast Bridging Fault Diagnosis using Logic Information

Abstract: In this paper, we present a diagnosis methodology targeting the whole set of bridging faults leading to either static or dynamic faulty behavior The adopted diagnosis algorithm resorts only to logic information provided by the tester without requiring a detailed description of the fault models It is based on an Effect-Cause analysis providing a ranked list of suspects always including the root cause of the observed error Experimental results on benchmarks ISCAS'89 and ITC '99 show the efficiency of the proposed solution in terms of diagnosis resolution and required computational time

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs

Abstract: In this paper, we present an analysis of resistive-open defects in the sense amplifier of SRAMs designed with the Infineon 65 nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been published in the past. This faulty behavior can be modeled as a dynamic two-cell Incorrect Read Fault (d2cIRF). Such d2cIRF is the consequence of a failure in the sense amplifier which prevents it to perform any read operations. We show that it requires a specific sequence of read operations to be detected. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior. Finally, a possible March test solution is presented to allow the detection of d2cIRFs in all sense amplifiers of an SRAM.

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window

Abstract: The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, the authors analyze the impact of a defective tunnel window oxide thickness. The authors show that this defective oxide thickness impacts erase or/and write operations as well as the retention and reliability of the eFlash. The proposed solution to detect such a defective oxide consists in using the voltage disturbance due to the coupling phenomenon existing between bit lines. This particular defective mechanism can be modeled as a coupling fault, especially a state coupling fault. Based on this analysis, the authors propose a test solution that uses two checkerboard patterns; checkerboard pattern (CKB) and its complement (CKBI). The authors show that these two patterns have to be applied by using a parallel programming approach, which allows to increase the coupling phenomenon and thus the voltage disturbance

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

Abstract: The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 mum eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the relevance of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis of actual defects presented in [1] we are then able to enhance existing test solutions for eFlash testing.

A concurrent approach for testing address decoder faults in eFlash memories

Abstract: The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line decoder or the bit line decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved; experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs.

Test et testabilité de structures numériques tolérantes aux fautes

Abstract: Les technologies submicroniques permettent aujourd'hui la realisation de circuits integres regroupant des milliards de transistors sur une meme puce. En prenant aussi en compte la miniaturisation croissante des procedes de fabrication et la complexite des nouveaux circuits integres (SoC, SiP), il est de plus en plus difficile de realiser un circuit integre sans aucun defaut de fabrication. Par consequent, le rendement de fabrication des circuits diminue et une diminution de plus en plus importante est a craindre pour les prochaines annees. Cette tendance est confirmee par l'ITRS (International Technology Roadmap for Semiconductors) [ITR07]. L'objectif de cette these est d'etudier la possibilite de realiser des structures numeriques de tolerance aux fautes afin d'augmenter le rendement de fabrication. En effet, bien que ces structures aient ete realisees pour assurer une certaine surete de fonctionnement lorsque le systeme est affecte par des fautes apparaissant pendant l'utilisation du circuit, plusieurs d'entre elles ont la capacite de tolerer aussi des defauts de fabrication. Dans ce manuscrit, un etat de l'art sur la tolerance aux fautes est realise. Puis, une architecture numerique tolerante aux fautes est choisie pour determiner sa capacite a augmenter le rendement de fabrication. Il s'agit de l'architecture TMR (Triple Modular Redundancy). Une procedure de test permettant d'evaluer sa tolerance aux fautes est decrite. Une amelioration de l'architecture TMR est ensuite proposee. Cette amelioration consiste a partitionner les modules en plusieurs parties independantes. Grâce a cela, les architectures TMR sont suffisamment tolerantes aux defauts de fabrication pour pouvoir ameliorer le rendement de fabrication. Le dernier chapitre de ce manuscrit concerne l'utilisation d'architectures TMR dans un contexte SoC. Plus le SoC contient de memoires, plus la realisation d'architectures TMR permet d'augmenter le rendement.