Jongjoo Shim

TL;DR: In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed, which decomposes the chip package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structure's impedance by using a segmentation method.

TL;DR: In this article, a simple circuital approach to evaluate the shielding effectiveness (SE) of rectangular enclosures with apertures is proposed, considering oblique incidence and polarization, and the scope of the proposed model is extended beyond 1 GHz, including higher order modes of the cavity.

TL;DR: In this paper, a 3D-TLM-based coupling model between through silicon via (TSV) and substrate based on a 3-dimensional transmission line matrix (3DTLM), which utilizes equivalent lumped circuit model of silicon substrate and TSV was proposed.

TL;DR: In this article, the authors introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN, which consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections.

TL;DR: The proposed on-chip eye opening monitor circuit with 4 ps time and 4 mv voltage resolutions can detect the maximum 6.4 Gbps data rate and give eye diagrams depending on on- chip high speed channel conditions.