The effect of back illumination with improved optical absorption has been analyzed for an ion-implanted GaAs OPFET considering the Pearson IV distribution of impurities. Plots have been made for two photo voltages developed across the substrate active layer junction and the Schottky junction. The drain-source current is significantly enhanced for the device when a fiber is inserted up to the active layer substrate junction compared with the case where the finite substrate effect is taken into account.

Analysis of GaAs OPFET with improved optical absorption under back illumination

Numerical study on the performance metrics of lightly doped drain and source graphene nanoribbon field effect transistors with double-material-gate

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket-implanted Double-Halo Dual-Material Gate (DHDMG) and Single-Halo Dual-Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual-material gate) to effectively suppress the short-channel effects (SCEs). The model is derived using the pseudo-2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual-material gate with single-halo and double-halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll-off than a pocket-implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.

Asymmetric halo and symmetric Single-Halo Dual-Material Gate and Double-Halo Dual-Material Gate n-MOSFETs characteristic parameter modeling

This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poissonpsilas equation in the depletion region at the surface Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature The result is compared with two other pocket profiles used to derive the threshold voltage models of n-MOSFETs The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices

Linear pocket profile based threshold voltage model for Sub-100 nm n-MOSFET incorporating substrate and drain bias effects

This paper presents an analytical 1/f noise model of fully overlapped lightly doped drain MOSFET incorporating the voltage drop in the n/sup -/ region due to the parasitic resistance. The FOLD structure has lesser noise effect than LDD MOSFET and the predicted results are verified with experimental data.

1/f noise model of fully overlapped lightly doped drain MOSFET

An analytical model for anomalous threshold voltage behavior of short channel MOSFETs

Cut off frequency and transit time analysis of lightly doped drain (LDD) MOSFETs

A computer aided model to optimize the performance of drain engineered MOS transistors is reported. Simple closed form expressions for the cut off frequency, transit time and gate current were derived. A comparative study of the device characteristics is made between the conventional, spacer LDD and Fully Overlapped LDD (FOLD) MOS transistors. Suitable fold finger designs were made to optimize the FOLD structures for higher cut off frequency, lower transit time and better current driveability. The computed cut off frequency of these devices is found to be in microwave region. The FOLD structure promises better performance and reliability in comparison with other structures.

Ciby Thomas

Papers

An analytical model for anomalous threshold voltage behavior of short channel MOSFETs

Cut off frequency and transit time analysis of lightly doped drain (LDD) MOSFETs

Optimization of Drain Engineered MOS Transistors for Microwave Frequency Applications

Optimization of High Performance Fully Overlapped LDD (FOLD) MOSFETs

New Threshold Voltage Model for an Ion Implanted GaAs MESFET