Showing papers in "Microelectronics Reliability in 1998"

TL;DR: Numerical examples show that genetic algorithms perform well for all the reliability problems considered in this paper, and some solutions obtained by genetic algorithms are better than previously best-known solutions.

TL;DR: A review of the most common dielectric reliability measurement methods can be found in this paper, where a broad number of different measurement techniques are described in detail for which the set up of the measurement and its stress parameters are clarified.

TL;DR: In this paper, the effect of ΔT and Tjmaz on the power cycling capability of IGBT dice was investigated by means of a matrix of stress cycles with different values of ΔTs and tjmax. Failure analysis has been performed to understand the failure mechanisms induced by the stress.

TL;DR: In this article, the effects due to the random fluctuation of the number of dopants in the MOSFET channel and the microscopic random distribution of dopant atoms in the channel were investigated.

TL;DR: In this article, the initiation and growth of cracks in the wire bond using finite element analysis was investigated for high voltage and high current power modules, which are key components for traction applications.

TL;DR: In this paper, the authors describe the state of the art of already existing reliability test as well as a proposal for accelerated power cycling and temperature cycling tests for railway traction applications, which are a result of the Brite EuRam research project RAPSDRA.

TL;DR: In this paper, a thermal failure analysis of passivated electronic devices with a sensitivity of 5 millikelvin by the use of a scanning thermal microscope (SThM) is presented.

TL;DR: In this article, three different, homogeneous, hot-electron induced degradation processes have been identified, with threshold voltages at 12,V, 7.5, and about 4.

TL;DR: In this article, the authors present a methodology for contact temperature measurements on chips surface in power cycling conditions and a fast 3D thermal simulation tool for multilayered hybrid or monolithic circuits.

TL;DR: In this paper, a mechanistic model is developed to account for an increase in activation energies for Al drift in the alloys in comparison to the pure metal, and good agreement is found between the model and the experiment.

TL;DR: In this paper, the failure mechanism of solder ball connect in chip scale package (CSP) utilizing wire-bonded ball grid array was elucidated using finite element analysis.

TL;DR: In this article, the authors investigated the thermally stable properties of cobalt and nickel silicides on crystalline Si (c-Si) and amorphous Si (a-Si).

TL;DR: Two different technologies serve as examples that the degree of correlation between ESD-failure currents obtained by transmission-line pulsing (TLP) and human body model (HBM) is a matter of the technology under investigation.

TL;DR: In this paper, the availability characteristics and reliability of a three-dissimilar-unit repairable system with two different repair facilities were investigated under some practical assumptions, and the explicit expressions of the following performance measures of the system were derived: (1) the pointwise and steady-state availability; (2) the failure frequency; (3) the renewal frequency; and (4) the reliability and the mean time to system failure.

TL;DR: In this paper, the need for ESD protection for high frequency devices and circuits is underlined by reviewing the compound semiconductor material properties with emphasis on ESD stress and by collecting their ESD failure thresholds.

TL;DR: In this article, a defect relaxation model under pulsed DC stress and a damage healing model under AC stress are developed, and electromigration design rules under these circumstances are proposed to ensure longer thermal migration lifetime under high frequency AC stress, to limit the temperature rise due to selfjoule heating.

TL;DR: In this paper, an analytical expression for both band-to-band and band-trap-band indirect tunnelings is used to study the gate-induced drain leakage (GIDL) current of MOSFETs measured before and after hot carrier stress.

TL;DR: The effectiveness of a good test methodology combined with a proper product design for screening at wafer sort latent defects of tunnel oxide is highlighted as a key factor for improving Flash memory reliability.

TL;DR: In this article, the authors examined and compared damage to n-channel and p-channel metal-oxide-silicon field effect transistors (MOSFETs) from direct current (d.c.) and alternating current (a.c).

TL;DR: In this article, a thin-film anodic silicon-to-silicon wafer bonding process was developed, where glass layers are deposited at 20 nm/s (1.2 μm/min) by electron-beam evaporation and bond strength in excess of 25 N/mm 2 for bonding temperatures higher than 300°C.

TL;DR: In this article, the effects of wire bonding parameters on bondability and ball bond reliability have been investigated by introducing the concept of a reduced bonding parameter (RBP), a combination of all bonding parameters.

TL;DR: In this article, the degradation of GaAlAs red light-emitting diodes was investigated under continuous and low-speed pulse operation, and the differences in the degradation and lifetime were clarified.

TL;DR: In this article, the dielectric constant and refractive index were found to depend on the thickness of the Ta 2 O 5 layers and a decreasing trend in the leakage current was found upon increasing oxidation temperature from 673 to 873 K.

TL;DR: In this article, power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and field effect transistor (FET) methods for each.

TL;DR: In this article, a wide range of activation energy values were obtained depending upon barrier layer (Ti or TiN), Cu deposition technique (PVD or CVD process) and grain size.

TL;DR: In this paper, the authors discuss simple descriptive analyses of wafer map data, as well as formal statistical methods, based on three different models that account for different spatial patterns and support the observed phenomenon that the faults are distributed non-uniformly across the wafer.

TL;DR: In this paper, the impact of semiconductor technology evolution and scaling of the epitaxial film, well design, isolation technology, MOSFET junctions, silicides, and interconnects on ESD robustness is addressed.

TL;DR: In this paper, the authors introduce techniques that have been developed to permit both full-chip power grid and signal net electromigration and Joule heating analysis, and provide feedback to the designer to permit easy design modification to provide superior long-tern reliability.

TL;DR: In this article, the authors present a shallow trench isolation (STI) process for sub-1/4 μm CMOS technologies with dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection.

TL;DR: In this paper, HBM ESD tests on two types of 0.6 μm DRAM devices showed that internal circuit or output driver failures would occur after the input or I/O pins were ESD stressed negative with respect to Vcc at ground.