Showing papers in "Microelectronics Reliability in 1998"

Genetic algorithms for reliability design problems

Abstract: This paper presents genetic algorithms for solving various reliability design problems, which include series systems, series–parallel systems and complex (bridge) systems. The objective is to maximize the system reliability, while maintaining feasibility with respect to three nonlinear constraints, namely, cost and weight constraints, and constraints on the products of volume and weight. In this paper, mixed-integer reliability problems are studied. Numerical examples show that genetic algorithms perform well for all the reliability problems considered in this paper. In particular, as reported, some solutions obtained by genetic algorithms are better than previously best-known solutions.

Dielectric Reliability Measurement Methods: A Review

Abstract: Reliability of thin dielectric films such as silicon dioxide grown on single crystalline silicon is of great importance for integrated circuits of present and future technologies. For the characterization of the quality of dielectric films, it is essential to have measurement methods available which can give a measure of dielectric reliability in a relatively short time. Stress biases are usually highly accelerated and cause destructive dielectric breakdown. Testing for dielectric reliability has been performed for more than 30 years, and in that time many different stress methods have been established. This article reviews that most common dielectric reliability measurement methods and gives practical guidelines to the reliability engineer in the field of dielectric characterization. The examples and data shown here are mainly from MOS gate oxides. The aim of this review paper is to emphasize advantages and disadvantages of the various stress methods. Appropriate dielectric stress methods are pointed out for applications such as process development, process characterization, pocess control and screening (burn-in). A broad number of different measurement techniques are described in detail for which the set up of the measurement and its stress parameters are clarified. Suitable dielectric test structures and the determination of the correct voltage and thickness of the dielectric are discussed; they are essential to determine the electric field across the thin film. The identification of dielectric breakdown and the interpretation and significance of the measurement results are reviewed. A good understanding of the stress method and the various measured parameters is essential to draw correct conclusions for the lifetime of the dielectric at operating conditions. The commonly used, basic analysis techniques for the measurement results are illustrated. Finally, the influence of stress-induced leakage currents on the dielectric reliability characterization is discussed and other aspects relating to very thin oxides of future technologies are briefly described. The paper also includes a large bibliography of more than 250 references.

On the effect of power cycling stress on IGBT modules

Abstract: IGBT reliability is becoming of great relevance, due to the range of application of these devices. Nevertheless, no standard test methods have been established, in order to evaluate their power cycling reliability. On this paper we report on the effect of ΔT and Tjmaz on the power cycling capability of IGBT dice, by means of a matrix of stress cycles with different values of ΔT and Tjmax. Failure analysis has been performed, in order to understand the failure mechanisms induced by the stress.

Discrete random dopant distribution effects in nanometer-scale MOSFETs

Abstract: In this paper, discrete random dopant distribution effects in nanometer-scale MOSFETs were studied using three-dimensional, drift-diffusion “atomistic” simulations. Effects due to the random fluctuation of the number of dopants in the MOSFET channel and the microscopic random distribution of dopant atoms in the MOSFET channel were investigated. Using a simplified model for the threshold voltage fluctuation due to dopant number fluctuation, we examine the standard deviations of the threshold voltage that can be expected for a highly integrated chip.

Crack mechanism in wire bonding joints

Abstract: High voltage and high current power modules are key components for traction applications. While the modules are exposed to harsh stress conditions all over their lifetime, high reliability is of decisive importance in this field of application. In power electronic packages wire bonding is used for the electrical interconnection from the chips to the output pins. Wire bond lift-off and solder fatigue are limiting the reliability. In this work we investigate the initiation and growth of cracks in the wire bonds using finite-element analysis.

Advanced IGBT modules for railway traction applications : Reliability testing

Abstract: IGBT modules for railway traction applications have to be more intensively tested then those for industrial application. The paper describes the state of the art of already existing reliability test as well as a proposal for accelerated power cycling and temperature cycling tests. These tests are a result of the Brite EuRam research project RAPSDRA (reliability of advanced power semiconductor devices for railway traction application).

Failure analysis of integrated devices by scanning thermal microscopy (SThM)

Abstract: High power densities dissipated in smaller and faster devices are leading to major thermal problems of semiconductor devices. The resulting local heat dissipation can induce deleterious effects like accelerated degradation or the destruction of the integrated circuits. Due to the shrinking feature sizes of modern devices and the small local extension of electrical failures the exact localization of these defects using established thermal failure analysis techniques like infrared thermometry becoming more and more difficult. Temperature measurements on passivated electronic devices with a sensitivity of 5 millikelvin by the use of a scanning thermal microscope (SThM) in contrast demonstrate the possibilities to use this system as a tool for failure analysis. Hot spot imaging with a spatial resolution of less than 150 nm, investigations on the backside of ULSI devices as well as a comparison with complementary established analysis techniques are presented.

Characterization of the hot-electron-induced degradation in thin SiO2 gate oxides

Abstract: With decreasing oxide thickness, some of the established methods to characterize oxide degradation become inapplicable because of limited sensitivity and because of direct tunneling which gives rise to large leakage currents through the oxide. However, new techniques are emerging which could not previously be used on thicker oxides, such as stress-induced leakage current measurements, current noise measurements, hot-electron emission microscopy, ballistic electron emission microscopy and hot-carrier luminescence. Some of these techniques provide unprecedented information on the local current densities with high spatial resolution and can be used to study inhomogeneous degradation in thin oxides at low voltages where homogeneous hot-carrier degradation becomes energetically unfavorable. In Si/SiO2/poly-Si structures, three different, homogeneous, hot-electron induced degradation processes have been identified, with threshold voltages at 12 V, 7.5 V and about 4 V. These are the generation of holes by impact ionization in the oxide, the injection of holes from the anode, and the release of hydrogen mostly from near the anode, respectively. The released hydrogen is very reactive and is responsible for the generation of many stress-induced defects. The existence of energy thresholds for homogeneous defect generation may limit the use of voltage acceleration for reliability evaluations.

Temperature measurements and thermal modeling of high power IGBT multichip modules for reliability investigations in traction applications

Abstract: To study the failure mechanisms induced on high power IGBT multichip modules by thermal cycling stress in traction environment, a good knowledge of the temperature distribution and variations on the chips and in the interfaces between the different layers of the packaging is necessary. This paper presents a methodology for contact temperature measurements on chips surface in power cycling conditions and a fast 3D thermal simulation tool for multilayered hybrid or monolithic circuits. The results of static and dynamic thermal simulation of a 1200A–3300V IGBT module are given and compared with the contact temperature measurements results. The investigation has been done within the RAPSDRA (Reliability of Advanced High Power Semiconductor Device for Traction Applications) European project.

Effects of alloying elements on electromigration

Abstract: Alloying elements, such as Cu, are used to reduce electromigration damage in miniaturized Al conductor lines. Nevertheless a thorough understanding of the fundamental mechanisms governing alloying effects has not been achieved yet. We present in situ drift experiments on pure Al and the alloys AlCu and AlMg and interpret them on the basis of activation energies. A mechanistic model is developed in order to account for an increase in activation energies for Al drift in the alloys in comparison to the pure metal. Good agreement is found between the model and the experiment.

Finite element analysis for solder ball failures in chip scale package

Abstract: The failure mechanism of solder ball connect in chip scale package (CSP) utilizing wire-bonded ball grid array was elucidated using finite element analysis in this study. The macro-micro-coupling technique was used in the current model. There exist two factors which contribute to solder ball cracking: shear stress due to thermal expansion mismatch between the package and the PCB and warpage of the package itself. This study revealed that shear stress due to the thermal expansion mismatch prevailed over warpage of the package in causing the solder ball cracking in the present type of CSP.

Thermal stability of cobalt and nickel silicides

Abstract: Thermal stability of cobalt and nickel silicides on crystalline Si (c-Si) and amorphous Si (a-Si) has been investigated. We have found that CoSi 2 is thermally stable on a-Si and c-Si substrates up to 950°C for 30 min. NiSi is stable and shows low resistivity on c-Si at around 700°C for 30 min, but is unstable on a-Si substrate even after annealing at 400°C.

Does the ESD-failure current obtained by transmission-line pulsing always correlate to human body model tests?

Abstract: Two different technologies serve as examples that the degree of correlation between ESD-failure currents obtained by transmission-line pulsing (TLP) and human body model (HBM) is a matter of the technology under investigation. Stressing a device with HBM or TLP can lead to different failure modes and, as a consequence, to a miscorrelation between the two test methods. Optimising a technology or a protection device only by means of TLP can easily lead to false conclusions.

Stochastic analysis of a repairable system with three units and two repair facilities

Abstract: This paper investigates the availability characteristics and the reliability of a three-dissimilar-unit repairable system with two different repair facilities. Under some practical assumptions, we obtain the explicit expressions of the state probabilities of the system and then the explicit expressions of the following performance measures of the system: (1) the pointwise and steady-state availability; (2) the pointwise and steady-state failure frequency; (3) the pointwise and steady-state renewal frequency; and (4) the reliability and the mean time to system failure.

ESD issues in compound semiconductor high-frequency devices and circuits

Abstract: The need of ESD protection for high frequency devices and circuits is underlined by reviewing the compound semiconductor material properties with emphasis on ESD stress and by collecting their ESD failure thresholds. Basic requirements for possible ESD protection structures in the microwave frequency regime are discussed and possible ESD protection devices and circuit concepts are proposed.

Electromigration under time-varying current stress

Abstract: Interconnect failure as a result of electromigration is one of the major IC reliability concerns. The continuing trend of scaling-down feature sizes has exacerbated this problem. Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed DC (local VCC and VSS lines) and bidirectional AC (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. The goal of this review is to clarify the failure mechanisms by examining different metallization systems (Al–Si, Al–Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under pulsed DC and AC stress in a wide frequency range (from millihertz to 500 MHz). Based on these experimental results, a defect relaxation model under pulsed DC stress and a damage healing model under AC stress are developed, and electromigration design rules under these circumstances are proposed. This review shows that in the circuit operating frequency range, the “design rule current” is the time-average current for both pulsed DC and AC cases. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.

Mechanism analysis of gate-induced drain leakage in off-state n-MOSFET

Abstract: An analytical expression for both band-to-band and band-trap-band indirect tunnelings is used to study the gate-induced drain leakage (GIDL) current of MOSFETs measured before and after hot-carrier stress. The voltage and temperature dependence of GIDL are characterized. Both results show that interface traps situated near the midgap participate in the conduction of GIDL, and band-trap-band indirect tunneling could be the major mechanism. This is further supported by the fact that the percentage increase in GIDL induced by hot-carrier stress is about the same as the corresponding increase in interface-trap density. On the other hand, under low-field conditions, trap-assisted Poole–Frenkle emission dominates over tunneling for temperatures even well below room temperature.

Flash memory reliability

Abstract: With reference to the mainstream technology, the most relevant failure mechanisms which affect yield and reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The effectiveness of a good test methodology combined with a proper product design for screening at wafer sort latent defects of tunnel oxide is highlighted as a key factor for improving Flash memory reliability. The degradation of device performance induced by program/erase cycling is discussed, covering both the behaviour of a typical cell and the evolution of memory array distribution. The erratic erasure phenomenon is illustrated as the most relevant mechanism reported so far to cause single bit failures in endurance tests. Finally, reliability implications of multilevel cell concepts are briefly analysed.

Damage to n-MOSFETs from electrical stress Relationship to processing damage and impact on device reliability

Abstract: The study reported herein examines and compares damage to n-channel and p-channel metal–oxide–silicon field-effect transistors (MOSFETs) from direct current (d.c.) and alternating current (a.c.) electrical stresses as well as the relationship of this damage to plasma processing damage in MOSFETs. The lightly-doped drain (LDD) MOSFETs used are of 0.5 μ m channel length and with a 90 A thick thermally grown gate oxide fabricated using a full flow CMOS process up to and including metal-1 processes and post-metallization annealing (PMA). The damage to MOSFETs is assessed using transistor parameter characterization and charge-to-breakdown measurements on the gate oxide. It is found that manifestations of d.c. stress-induced damage and a.c. stress-induced damage to transistors are fairly similar in that both forms of damage are passivated by PMA and are reactivated by a subsequent d.c. electrical stress. However, a.c. stress-induced damage is observed to occur at much lower electric fields across the gate oxide than those necessary for d.c. stress-induced damage to be significant. This is attributed to a.c. currents, caused by carrier hopping, occurring at relatively low electric fields. One implication of our results is that plasma-charging damage, often attributed to d.c. electrical stress alone, may comprise an a.c. electrical stress component too.

Reliability of industrial packaging for microsystems

Abstract: Packaging concepts for silicon-based micromachined sensors exposed to harsh environments are explored. By exposing the sensors directly to the media and applying protection at the wafer level the packaging and assembly will be simplified as compared to conventional methods of fabrication. Protective coatings of amorphous silicon carbide and tantalum oxide are suitable candidates with etch rates below 0.1 A/h in aqueous solutions with pH 11 at temperatures up to 140°C. Si-Ta-N films exhibit etch rates around 1 A/h. Parylene C coatings did not etch but peeled off after extended exposure times at elevated temperatures. The best diamond-like carbon films we tested did not etch, but delaminated due to local penetration of the etchants. Several glue types were investigated for chip mounting of the sensors. Hard epoxies, such as Epotek H77, on the one hand exhibit high bond strength and least degradation and leakage, but on the other hand introduce large sensor output drift with temperature changes. Softening of the Epo-tek H77 was observed at 70°C. An industrially attractive thin-film anodic silicon-to-silicon wafer bonding process was developed. Glass layers are deposited at 20 nm/s (1.2 μm/min) by electron-beam evaporation and bond strengths in excess of 25 N/mm 2 are obtained for bonding temperatures higher than 300°C. Through-hole electrical feedthroughs with a minimum line width of 20μm and a density of 250 wires per cm were obtained by applying electro-depositable photo-resist. Hermetically sealed feedthroughs were obtained using glass frits, which withstand pressures of 4000 bar.

A concept to relate wire bonding parameters to bondability and ball bond reliability

Abstract: The effects of wire bonding parameters on bondability and ball bond reliability have been investigated. Bondability is characterized by ball shear stress (ball shear force per unit area) and ball bond reliability by median time to failure during in-situ ball bond degradation measurements. By introducing the concept of a reduced bonding parameter (RBP), a combination of all bonding parameters, we are able to relate the bonding parameters to bondability and ball bond reliability. With the appropriate RBP, ball shear force, ball shear stress, andball bond reliability appear to be well-behaved functions of the RBP fora wide range of settings. This provides us with simple analytical tool for optimizing bonding parameter windows.

The degradation of GaAlAs red light-emitting diodes under continuous and low-speed pulse operations

Abstract: Long-term accelerated degradation tests on GaAlAs red light-emitting diodes were performed under continuous and low-speed pulse operation, and the differences in the degradation and lifetime were clarified. The major factor causing the degradation was suggested to be the decrease in the radiative recombination probability due to defect generation.

Electrical properties of thin Ta2O5 films obtained by thermal oxidation of Ta on Si

Abstract: Tantalum pentoxide films (13–260 nm) on p-type Si have been prepared by thermal oxidation at 673–873 K of rf sputtered Ta films and have been studied using Al–Ta 2 O 5 –Si capacitors. Both dielectric constant and refractive index were found to depend on the thickness of the Ta 2 O 5 layers. Layers with a dielectric constant of 25–32 were obtained. A decreasing trend in the leakage current was found upon increasing oxidation temperature from 673 to 873 K. Leakage current density of (10 −8 to 3×10 −7 ) A cm −2 at 1 MV cm −1 effective field was achieved.

Electromigration failure modes in damascene copper interconnects

Abstract: Electromigration experiments were performed on passivated damascene copper interconnects with 1 μm linewidth. A wide range of activation energy values were obtained depending upon barrier layer (Ti or TiN), Cu deposition technique (PVD or CVD process) and grain size. An activation energy of 1.1 eV was measured in PVD-Cu layers leading to significant improvement over AlCu technology: lifetime at 140°C was about 2 orders of magnitude longer. Furthermore, SEM pictures after line failure emphasized interface diffusion mechanisms which occurred in these structures for both Cu CVD and PVD deposition processes.

Designing power supply clamps for electrostatic discharge protection of integrated circuits

Abstract: Power supply electrostatic discharge (ESD) clamping is needed to protect the IC power supply as well as to provide convenient discharge paths for ESD currents, and thereby simplify the total design problem. A variety of methods are reviewed and explored, notably those employing diodes or field effect transistor (FETs) built in bulk complementary metal-oxide semiconductor (CMOS) technology and avoiding avalanche behavior. Power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and FET methods for each. Designs extend to clamping for mixed voltage supplies on a single chip, including power supplies above the gate oxide tolerance. New designs and results for power clamps based on PMOS FETs are presented for the first time.

Use of wafer maps in integrated circuit manufacturing

Abstract: A wafer map identifies the locations of defective integrated circuits (chips) on a silicon wafer and provides important spatial information. The wafer yield is a useful measure of the process quality, but other features are necessary to account for. Careful statistical analysis addressing the spatial information in the wafer map is necessary in order to monitor the quality of the manufacturing process, and identify/eliminate fault sources with assignable causes. We discuss simple descriptive analyses of wafer map data, as well as formal statistical methods, based on three different models that account for different spatial patterns. In particular, the models support the observed phenomenon that the faults are distributed non-uniformly across the wafer, by allowing the fault probability to vary across the wafer, and allowing faults at adjacent locations to be statistically dependent.

The impact of MOSFET technology evolution and scaling on electrostatic discharge protection

Abstract: MOSFET (metal-oxide silicon field effect transistor) evolution and technology scaling impacts electrostatic discharge (ESD) protection networks, design and strategy. The continous evolution of semiconductor processing forces new issues to arise for each technology generation and the evolution of MOSFET structures in each generation requires re-addressing of the scaling implications on ESD robustness. This paper addresses the impact of semiconductor technology evolution and scaling of the epitaxial film, well design, isolation technology, MOSFET junctions, silicides, and interconnects on ESD robustness. The scaling of the epitaxial film thickness and p++ vs p− substrate influences the ESD robustness of n-channel MOSFET and diode-based ESD protection networks. ESD diode elements show a 2× to 3× improvement in thin p− epitaxy on a p++ wafer compared to p−substrates. The evolution from diffused wells to MeV-implanted retrograde well designs have shown that the parasitic vertical bipolar transistor plays a lesser role in ESD protection networks compared to the diode action. A 3× HBM (human body model) ESD improvement is demonstrated using advanced high dose MeV retrograde well implants. Isolation technology has an influence on the high voltage electrical parametrics, lateral parasitics, thermal transport and semiconductor process integration with the MOSFET junction and silicide film. The transition from LOCOS to STI (shallow trench isolation) significantly altered the electrical parametrics, failure mechanisms, and ESD networks. The MOSFET-junction evolution from Ldd, dual-Ldd, abrupt junctions to “extension implants” and how this influenced integration and ESD robustness is discussed. MOSFET junctions, salicide, and STI integration issues, such as STI pull-down, can influence the ESD robustness of ESD diode structures. Althernative salicide processes (e.g. cobalt), deep B11 implants and novel poly-silicon-bound diode structures demonstrate 3× improvement in HBM ESD robustness. As technology transitions from aluminum- to copper-based interconnect systems, interconnect wire (2× improvement) and via (3× improvement) ESD improvements are demonstrated. As a result of power supply scaling, the impact of technology scaling on ESD networks, peripheral I/O driver circuits and receiver networks, and how it influences the ESD protection of advanced semiconductor chips is shown. Power-supply scaling, noise issues and multichip systems has led to increasing complexity and importance of sequence-independent ESD networks, ESD networks between power supplies and ESD power clamps. Receiver and I/O driver designs have also evolved due to the MOSFET dielectric scaling and ESD robustness requirements. Technology generation evolution of peripheral driver circuits evolution demonstrates the need for local resistor ballasting of driver circuits. With MOSFET scaling, receiver circuit pass transistors, keeper feedback and zero-Vt devices introduce new ESD issues and receiver design complexity. MOSFET scaling requires ESD power clamps across core and peripheral supplies to reduce the current loop impedance for high frequency applications. MOSFET scaling also has led technology to have a future interest in high-frequency semiconductor devices, such as rf-CMOS, silicon-on-insulator, and SiGe-based devices. Novel SOI ESD networks, such as polysilicon-bound diodes and body- and gate-coupled SOI ESD networks, demonstrate excellent ESD results in advanced CMOS-on-SOI technologies.

Full-chip reliability analysis

Abstract: Reliability analysis has not been promoted to the realm of full-chip because techniques to extract, manage, and process full-chip power grid and signal data have not been previously available. This paper introduces techniques that have been developed to permit both full-chip power grid and signal net electromigration and Joule heating analysis. Results of this analysis provide feedback to the designer to permit easy design modification to provide superior “designed-in” long-tern reliability.

STI process steps for sub-quarter micron CMOS

Abstract: This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μm CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated.

Unique ESD failure mechanisms during negative to Vcc HBM tests

Abstract: HBM ESD tests on two types of 0.6 μ m DRAM devices showed that internal circuit or output driver failures would occur after the input or I/O pins were ESD stressed negative with respect to Vcc at ground. These failures occurred at lower than expected ESD stress voltages due to power-up circuit interactions that either turned-on unique internal parasitic ESD current paths or disrupted the normal operation of the output pin’s ESD protection circuit. ESD analysis found there exists a set of power-up sensitive circuits and if placed near a Vcc bond pad can result in low voltage ESD failures.