This article proposes a health indicator estimation method based on the digital-twin concept aiming for condition monitoring of power electronic converters. The method is noninvasive, without additional hardware circuits, and calibration requirements. An application for a buck dc–dc converter is demonstrated with theoretical analyses, practical considerations, and experimental verifications. The digital replica of an experimental prototype is established, which includes the power stage, sampling circuit, and close-loop controller. Particle swarm optimization algorithm is applied to estimate the unknown circuit parameters of interest based on the incoming data from both the digital twin and the physical prototype. Cluster-data of the estimated health indicators under different testing conditions of the buck converter is analyzed and used for observing the degradation trends of key components, such as capacitor and MOSFET. The outcomes of this article serve as a key step for achieving noninvasive, cost-effective, and robust condition monitoring for power electronic converters.

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A Digital Twin Based Estimation Method for Health Indicators of DC–DC Converters

This Review highlights basic and transition metal conducting and semiconducting oxides. We discuss their material and electronic properties with an emphasis on the crystal, electronic, and band structures. The goal of this Review is to present a current compilation of material properties and to summarize possible uses and advantages in device applications. We discuss Ga2O3, Al2O3, In2O3, SnO2, ZnO, CdO, NiO, CuO, and Sc2O3. We outline the crystal structure of the oxides, and we present lattice parameters of the stable phases and a discussion of the metastable polymorphs. We highlight electrical properties such as bandgap energy, carrier mobility, effective carrier masses, dielectric constants, and electrical breakdown field. Based on literature availability, we review the temperature dependence of properties such as bandgap energy and carrier mobility among the oxides. Infrared and Raman modes are presented and discussed for each oxide providing insight into the phonon properties. The phonon properties also provide an explanation as to why some of the oxide parameters experience limitations due to phonon scattering such as carrier mobility. Thermal properties of interest include the coefficient of thermal expansion, Debye temperature, thermal diffusivity, specific heat, and thermal conductivity. Anisotropy is evident in the non-cubic oxides, and its impact on bandgap energy, carrier mobility, thermal conductivity, coefficient of thermal expansion, phonon modes, and carrier effective mass is discussed. Alloys, such as AlGaO, InGaO, (Al xIn yGa1− x− y)2O3, ZnGa2O4, ITO, and ScGaO, were included where relevant as they have the potential to allow for the improvement and alteration of certain properties. This Review provides a fundamental material perspective on the application space of semiconducting oxide-based devices in a variety of electronic and optoelectronic applications.

A review of band structure and material properties of transparent conducting and semiconducting oxides: Ga2O3, Al2O3, In2O3, ZnO, SnO2, CdO, NiO, CuO, and Sc2O3

Power utilities are struggling to reduce power failure incidents in substations and their components to operate more reliably and economically [1]. Many power failures are produced directly or indirectly because of the insulation system of utility components [2], [3]. The selection of the insulation should ensure power plant operational continuity along with completely resolving or significantly limiting the actual power system's failures [4]. Gas insulated substations (GIS) have the best insulation performance which ensures achieving minimum failure incidents, although at high installation cost. The most common insulating gas used in GIS is Sulfur hexafluoride (SF 6 ) gas, which is widely used as an effective electrical insulation as well as an arc-quenching medium [5]. Basic GIS and gas insulated transmission lines (GITL or GIL) consist of a conductor supported by solid insulators inside an enclosure filled with SF 6 gas or its mixture [6].

Partial discharge detection and diagnosis in gas insulated switchgear: State of the art

GaN technology is not only gaining traction in power and RF electronics but is also rapidly expanding into other application areas including digital and quantum computing electronics. This paper provides a glimpse of future GaN device technologies and advanced modeling approaches that can push the boundaries of these applications in terms of performance and reliability. While GaN power devices have recently been commercialized in the 15–900 V classes, new GaN devices are greatly desirable to explore both higher-voltage and ultra-low-voltage power applications. Moving into the RF domain, ultra-high frequency GaN devices are being used to implement digitized power amplifier circuits, and further advances using the hardware–software co-design approach can be expected. On the horizon is the GaN CMOS technology, a key missing piece to realize the full-GaN platform with integrated digital, power, and RF electronics technologies. Although currently a challenge, high-performance p-type GaN technology will be crucial to realize high-performance GaN CMOS circuits. Due to its excellent transport characteristics and ability to generate free carriers via polarization doping, GaN is expected to be an important technology for ultra-low temperature and quantum computing electronics. Finally, given the increasing cost of hardware prototyping of new devices and circuits, the use of high-fidelity device models and data-driven modeling approaches for technology-circuit co-design are projected to be the trends of the future. In this regard, physically inspired, mathematically robust, less computationally taxing, and predictive modeling approaches are indispensable. With all these and future efforts, we envision GaN to become the next Si for electronics.

Emerging GaN technologies for power, RF, digital, and quantum computing applications: Recent advances and prospects

Ga2O3 power diodes with high voltage/current ratings, superior dynamic performance, robust reliability, and potentially easy-to-implement are a vital milestone on the Ga2O3 power electronics roadmap. In this letter, a better tradeoff between fast reverse-recovery and rugged surge-current capability has been demonstrated in NiO/Ga2O3 p-n heterojunction diodes (HJDs). With the double-layered p-NiO design, the HJD exhibits superior electrostatic performances, including a high breakdown voltage of 1.37 kV, a forward current of 12.0 A with a low on-state resistance of 0.26 Ω, yielding a static Baliga's figure of merit (FOM) of 0.72 GW/cm2. Meanwhile, the fast switching performance has been observed with a short reverse recovery time in nanosecond timescale (11 ns) under extreme switching conditions of d i /d t up to 500 A/μs. In particular, for a 9-mm2 HJD, a large surge current of 45 A has also been obtained in a 10-ms surge transient, thanks to the conductivity modulation effect. These results are comparable with those of the advanced commercial SiC SBDs and have significantly outperformed the past reported Ga2O3 HJDs, fulfilling the enormous potential of Ga2O3 in power applications.

1.37 kV/12 A NiO/β-Ga 2 O 3 Heterojunction Diode With Nanosecond Reverse Recovery and Rugged Surge-Current Capability

An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. These results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

This work describes the high-temperature performance and avalanche capability of normally- off 1.2-K V-CLASS vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage ( ${V}_{\text {TH}}$ ) is over 2 V with less than 0.15 V shift from 25 °C to 200 °C. The specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) increases from 0.82 at 25 °C to 1.8 $\text{m}\Omega \cdot $ cm2 at 200 °C. The thermal stability of ${V}_{\text {TH}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}$ are superior to the values reported in SiC MOSFETs and JFETs. At 200 °C, the gate leakage and drain leakage currents remain below $100~\mu \text{A}$ at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole–Frenkel (PF) emission model. An avalanche breakdown voltage ( $BV_{\!\!\text {AVA}}$ ) with positive temperature coefficient is shown in both the quasi-static ${I}$ – ${V}$ sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a $BV_{\!\!\text {AVA}}$ over 1700 V and a critical avalanche energy ( ${E}_{\text {AVA}}$ ) of 7.44 J/cm2, with the ${E}_{\text {AVA}}$ comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications.

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1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

Aging precursor identification is crucial to achieving online condition monitoring and estimating the remaining lifetime of insulated-gate bipolar transistors (IGBTs). However, existing failure precursors are limited with respect to in situ monitoring. In this paper, the duration of the Miller plateau during the IGBT turn- on transition is proposed as an online precursor indicating two dominant types of failures. Based on the theoretical closed-form expressions, the adverse effects of package-related bond wire fatigue and chip-related gate oxide degradation on the Miller plateau duration are explained. By using a dedicated online measurement system that is implemented on the gate driver side, the proposed precursor is extracted during operation. Discrete IGBTs of two gate structures are employed during the accelerated aging tests. Negative and positive degradation trends of the Miller plateau duration under power cycling and high electric field stress, respectively, are revealed, thus illustrating the validity of the proposed method. Finally, the main differences in physics-of-failure between two types of aged devices are investigated using post-failure analysis. The innovation of applying the Miller plateau duration as a failure precursor involves its ability to accomplish real-time field monitoring and its sensitivity to multiple failure mechanisms.

In situ Condition Monitoring of IGBTs Based on the Miller Plateau Duration

This work, for the first time, demonstrates a 1.2-kV-class, 4-A normally-off vertical GaN fin-channel JFET on GaN substrate, and characterizes its static and dynamic performance as well as avalanche robustness. The device shows an on/off current ratio of ~109, a specific on-resistance (R ON ) of 0.82 mΩ·cm2, and a threshold voltage (V TH ) over 0.5 V extracted at a drain current of 1 mA. The on/off ratio and V TH exhibit very little changes at high temperatures up to 125°C. A robust avalanche is observed under the unclamped inductive switching (UIS) conditions, showing an avalanche breakdown voltage (BV AVA ) of 1470 V and an avalanche current (I AVA ) over 1 A. The I AVA is found to mainly flow through the p-GaN gate instead of the n-GaN fins. The JFET also shows small junction capacitances. Double-pulse tests at 600-V/4-A reveal a rise/fall time of 12.9 ns/10.3 ns and a total loss of 37 μJ. Almost no reverse recovery is observed on the body diode, due to the short lifetime of minority carriers. To the best of our knowledge, we report one of the highest Baliga’s figure-of-merit (BV2/R ON ) and the first avalanche robustness in vertical GaN power transistors. Our results suggest the great potential of vertical GaN JFETs for medium-voltage high-frequency power applications.

1.2 kV Vertical GaN Fin JFETs with Robust Avalanche and Fast Switching Capabilities

The unique gate failure mode of SiC MOSFETs is often identified but has not been fully understood yet. In this letter, post-failure cell inspections demonstrate that its main cause is the crack at the SiO2 dielectric layer with melted source aluminum inside. An electro-thermal-mechanical simulation is performed to reproduce the failure transition, and it reveals that the crack forms at an early stage. This new failure mechanism further enlightens on the vulnerability of the vertical power MOSFET structure in extremely high-temperature operation.

Jingcun Liu

Papers

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

In situ Condition Monitoring of IGBTs Based on the Miller Plateau Duration

1.2 kV Vertical GaN Fin JFETs with Robust Avalanche and Fast Switching Capabilities

Gate Failure Physics of SiC MOSFETs Under Short-Circuit Stress