Proceedings ArticleDOI
A novel low-power readout structure for TDI ROIC
Lu Wengao,Gao Jun,Chen Zhongjian,Liu Jing Liu Jing,Cui Wentao,Tang Ju,Ji Lijiu +6 more
- pp 591-594
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TLDR
A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented, which can increase the column OPA's smallest settling time without decreasing frame's readout frequency.Abstract:
A novel readout structure called Forward-Backward-Asynchronous-Reset (FBAR) structure is presented in this paper. This readout structure is used in high performance CMOS readout integrated circuits (ROIC). Using asynchronous reset structure can increase the column OPA's smallest settling time without decreasing frame's readout frequency. By increasing smallest settling time, a low-power column OPA with power dissipation=78 mW can satisfy fast readout speed. While in typical synchronous reset structure, the column OPA's power dissipation may exceed 200 mW to meet readout speed. This improvement can save more than 50% power dissipation of the column readout stage. An experiment ROIC chip using FBAR structure has been fabricated with 1.2 mm DPDM n-well CMOS technology. Testing result shows the total active chip power dissipation is 25 mW.read more
Citations
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Journal ArticleDOI
Time-Delay-Integration Architectures in CMOS Image Sensors
TL;DR: In this article, the authors studied the difficulty and challenges of implementing time-delay integration (TDI) functionality in a CMOS technology, including synchronization of the samples forming a TDI pixel, adder matrix outside the array, and addition noise.
Patent
Automated conversion of synchronous to asynchronous circuit design representations
TL;DR: In this paper, a synchronous netlist may be generated from a single-input single-output (SISO) synchronous circuit design and then converted to an asynchronous circuit design.
Proceedings ArticleDOI
The study of dual-window random addressable ROIC
Lu Wengao,Chen Zhongjian,Gao Jun,Liu Dan,Tang Ju,Song Ying,Liu Jing Liu Jing,Cui Wentao,Ji Lijiu +8 more
TL;DR: A novel dual-window readout structure is presented that ROIC can readout two sub-arrays synchronously in windowing mode, which allows image system to trace two fast moving objects without using two ROICs.
Patent
Reset mechanism conversion
TL;DR: In this article, a replicated reset token at a fraction of the operational frequency of the reset signal is distributed to the locations of the asynchronous dataflow logic blocks, where the reset token can be used to communicate with the corresponding data flow logic blocks.
Patent
Converting a synchronous circuit design into an asynchronous design
TL;DR: In this paper, a method for converting a synchronous circuit design to an asynchronous dataflow design is described, based on functional characteristics of the synchronous logic blocks and connection boxes.
References
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Proceedings ArticleDOI
An improved low power CMOS readout circuit for focal plane array
TL;DR: An improved low power CMOS snapshot readout structure called OESCA (Odd-Even Snapshot Charge Amplifier) for focal plane array (FPA) is presented in this article.