This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

This work is a contribution to a drastic change in standard signal processing chains. The main objective is to reduce the power consumption by one or two orders of magnitude. Integrated Smart Devices and Communicating Objects are application domains targeted by this work. In this context, we present a new class of Analog-to-Digital Converters (ADCs), based on an irregular sampling of the analog signal, and an asynchronous design. Because they are not conventional, a complete design methodology is presented. It determines their characteristics given the required effective number of bits and the analog signal properties. it is shown that our approach leads to a significant reduction in terms of hardware complexity and power consumption. A prototype has been designed for speech applications, using the STMicroelectronics 0.18-/spl mu/m CMOS technology. Electrical simulations prove that the factor of merit is increased by more than one order of magnitude compared to synchronous Nyquist ADCs.

A new class of asynchronous A/D converters based on time quantization

Introduction to Reconfigurable Computing provides a comprehensive study of the field Reconfigurable Computing. It provides an entry point to the novice willing to move in the research field reconfigurable computing, FPGA and system on programmable chip design. The book can also be used as teaching reference for a graduate course in computer engineering, or as reference to advance electrical and computer engineers. It provides a very strong theoretical and practical background to the field of reconfigurable computing, from the early Estrins machine to the very modern architecture like coarse-grained reconfigurable device and the embedded logic devices. Apart from the introduction and the conclusion, the main chapters of the book are Architecture of reconfigurable systems, Design and implementation, High-Level Synthesis for Reconfigurable Devices, Temporal placement, On-line and Dynamic Interconnection, Designing a reconfigurable application on Xilinx Virtex FPGA, System on programmable chip, Applications.

Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications

Single-clocked digital systems are largely a thing of the past. Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. Using an asynchronous interconnect decouples the timing issues for the separate blocks. Systems employing such schemes are called globally asynchronous, locally synchronous (GALS). To minimize time to market, large SoC designs must integrate many functional blocks with minimal design effort. These blocks are usually designed using standard synchronous methods and often have different clocking requirements. A GALS approach can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. SoCs may also achieve power savings by clocking different blocks at their minimum speeds. For example, Scott et al. describe the advantages of GALS design for an embedded-processor peripheral bus.

https://www.ece.ubc.ca/~lemieux/publications/teehan-ieeedtcomputer2007.pdf

A Survey and Taxonomy of GALS Design Styles

We derive the criteria for deflagration to detonation transition (DDT) in a Type Ia supernova. The theory is based on two major assumptions: (1) detonation is triggered via the Zeldovich gradient mechanism inside a region of mixed fuel and products, and (2) the mixed region is produced by a turbulent mixing of fuel and products either inside an active deflagration front or during the global expansion and subsequent contraction of an exploding white dwarf. We determine the critical size of the mixed region required to initiate a detonation in a degenerate carbon-oxygen mixture. This critical length is much larger than the width of the reaction front of a Chapman-Jouguet detonation. However, at densities greater than 5 × 106 g cm-3, it is much smaller than the size of a white dwarf. We derive the critical turbulent intensity required to create the mixed region inside an active deflagration front in which a detonation can form. We conclude that the density ρtr at which a detonation can form in a carbon-oxygen white dwarf is low, less than 2-5 × 107 g cm-3 but greater than 5 × 106 g cm-3.

https://iopscience.iop.org/article/10.1086/303815/pdf

Deflagration-to-Detonation Transition in Thermonuclear Supernovae

Todays networks of processors on and off chip, operating with independent clocks, need effective synchronization of the data passing between them for reliability. When two or more processors request access to a common resource, such as a memory, an arbiter has to decide which request to deal with first. Current developments in integrated circuit processing are leading to an increase in the numbers of independent digital processing elements in a single system. With this comes faster communications, more networks on chip, and the demand for more reliable, more complex, and higher performance synchronizers and arbiters. Written by one of the foremost researchers in this area of digital design, this authoritative text provides in-depth theory and practical design solutions for the reliable working of synchronization and arbitration hardware in digital systems. The book provides methods for making real reliability measurements both on and off chip, evaluating some of the common difficulties and detailing circuit solutions at both circuit and system levels. Synchronization and Arbitration in Digital Systems also presents: mathematical models used to estimate mean time between failures in digital systems; a summary of serial and parallel communication techniques for on-chip data transmission; explanations on how to design a wrapper for a locally synchronous cell, highlighting the issues associated with stoppable clocks; an examination of various types of priority arbiters, using signal transition graphs to show the specification of different designs (from the simplest to more complex multi-way arbiters) including ways of solving problems encountered in a wide range of applications; essential information on systems composed of independently timed regions, including a discussion on the problem of choice and the factors affecting the time taken to make choices in electronics. With its logical approach to design methodology, this will prove an invaluable guide for electronic and computer engineers and researchers working on the design of digital electronic hardware. Postgraduates and senior undergraduate students studying digital systems design as part of their electronic engineering course will struggle to find a resource that better details the information given inside this book

Synchronization and Arbitration in Digital Systems

The paper presents asynchronous design solutions to the problem of Priority Arbitration which is defined in the following form. A system consists of multiple, physically concurrent, processes with a shared resource. The discipline of resource allocation is a function of parameters of the active requests, which are assigned to the requests either statically or dynamically. This function can be defined in an (arbitrary) combinatorial way (contrary to conventional, 'topological', mappings, such as that used in a daisy-chain arbiter). The proposed designs are quasi-speed-independent. Furthermore, the priority logic, in the dynamic case, has the following architectural feature: it is a tree structure in which the control flow is maximally decoupled from the data-path by means of an early propagation of the 'valid'-'invalid' signals, concurrently, with processing the priority data. This lends to significant reduction in the overall arbitration delay when the number of active requests is low.

Priority arbiters

There is considerable interest at present in the design of asynchronous systems based on the use of self-timing components for arithmetic and other operations. Amongst the advantages claimed for asynchronous design are ease of design, high speed, low power, and device speed independence. An often quoted example of the speed improvement possible from self-timed hardware is parallel binary addition, where the carry signals in the worst case must propagate through n stages before the sum can be guaranteed correct. In practice, however, it is not possible to achieve significant speed advantage from the method, and this paper shows that asynchronous adders only give a performance improvement over more conventional hardware in very limited conditions, where the size and regularity of the layout are at a premium.

An evaluation of asynchronous addition

A deep metastability measurement scheme has been implemented on chip using digital circuits with 0.18 mum technology. Compared with previous off-chip implementations using analog circuits, the on-chip implementation allows integration of both the synchronizer circuits and the measurement method, and eliminates high-speed off-chip paths which are a source of inaccuracy. It also makes control at the picosecond level easier because of the inherent stability of digital integrating counters and digital delay lines. Our results show that the digital delay line used to adjust the data to clock times is controllable to an increment of 0.1 ps, and the input time distribution is 5.2 ps compared with 7.6 ps for the analog version. Because of the use of high and low counters, we can control the ratio of high to low outputs so that the actual input distribution can be measured to within better than 1 ps. The metastability time constant tau has been measured down to 10-17 s which corresponds to an mean time between failures (MTBF) of 100 seconds in an experimental time of 10 minutes and can be extended to a lower level by increasing the measurement time. Our results also show that a new synchronizer circuit designed for robustness to variation in Vdd performed at least as well as the Jamb Latch at all values of Vdd, and is more than 20% faster when Vdd was reduced by 25%.

https://www.eprints.ncl.ac.uk/file_store/production/56546/9CDE25B5-A101-4C79-A022-EF8642427CFB.pdf

D.J. Kinniment

Papers

Synchronization and Arbitration in Digital Systems

Priority arbiters

An evaluation of asynchronous addition

On-Chip Measurement of Deep Metastability in Synchronizers

Modelling, analysis and synthesis of asynchronous control circuits using Petri nets