G. Russell

TL;DR: A circuit is described that is aimed at reliably amplifying edge time differences by a factor between 3 and 10 before measurement to enable greater accuracy.

TL;DR: A deep metastability measurement scheme has been implemented on chip using digital circuits with 0.18 mum technology, and a new synchronizer circuit designed for robustness to variation in Vdd performed at least as well as the Jamb Latch at all values of Vdd.

TL;DR: This book will help you bring the advanced simulation and test methodologies for vlsi design book to you much easier.

TL;DR: Two high-resolution time measurement schemes for digital BIST applications, namely: two-delay interpolation method (TDIM) and time amplifier are presented, which offer two main advantages: a low range of timing measurement which has never been achieved before, and a small size of layout occupying 0.2 mm/sup 2/ or equivalent to 3020 transistors.

TL;DR: Methods of extending the measurement range are described, in which the number of metastable events generated is increased by four orders of magnitude, and events with long metastable times are selected from the large number of more normal events.