In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

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Active pixel sensor with intra-pixel charge transfer

The biomimetic CMOS dynamic vision and image sensor described in this paper is based on a QVGA (304×240) array of fully autonomous pixels containing event-based change detection and pulse-width-modulation (PWM) imaging circuitry. Exposure measurements are initiated and carried out locally by the individual pixel that has detected a change of brightness in its field-of-view. Pixels do not rely on external timing signals and independently and asynchronously request access to an (asynchronous arbitrated) output channel when they have new grayscale values to communicate. Pixels that are not stimulated visually do not produce output. The visual information acquired from the scene, temporal contrast and grayscale data, are communicated in the form of asynchronous address-events (AER), with the grayscale values being encoded in inter-event intervals. The pixel-autonomous and massively parallel operation ideally results in lossless video compression through complete temporal redundancy suppression at the pixel level. Compression factors depend on scene activity and peak at ~1000 for static scenes. Due to the time-based encoding of the illumination information, very high dynamic range - intra-scene DR of 143 dB static and 125 dB at 30 fps equivalent temporal resolution - is achieved. A novel time-domain correlated double sampling (TCDS) method yields array FPN of 56 dB (9.3 bit) for >10 Lx illuminance.

A QVGA 143 dB Dynamic Range Frame-Free PWM Image Sensor With Lossless Pixel-Level Video Compression and Time-Domain CDS

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-/spl mu/m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 /spl mu/m/spl times/40 /spl mu/m with 26% fill-factor. Array sizes of 28/spl times/28 elements and 128/spl times/128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 /spl mu/V/e/sup -/ for the p-well devices and 6.5 /spl mu/V/e/sup -/ for the n-well devices. Input referred read noise of 28 e/sup -/ rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed.

CMOS active pixel image sensors for highly integrated imaging systems

Single substrate device is formed to have an image acquistition device and a controller. The controller on the substrate controls the system operation.

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CMOS active pixel sensor type imaging system on a chip

The characterization of surface channel charge-coupled device line imagers with front-surface imaging, interline transfer, and 2-phase stepped oxide, silicon-gate CCD registers is presented. The analysis, design, and evaluation of 1/spl times/64 CCD line arrays are described in terms of their performance at low light levels. The authors describe the responsivity, resolution, spectral, and noise measurements on silicon-gate CCD sensors and CCD interline shift-registers. The influence of transfer inefficiency and electrical fat-zero insertion on resolution and noise is described at low light levels.

Characterization of surface channel CCD image arrays at low light levels

A CCD adaptive signal processor is described which uses a so-called `clipped-data' least mean square (LMS) error algorithm to optimize the selection of tap weights in a CCD filter. A detailed description of a 16-tap monolithic silicon CCD analog adaptive filter is also presented. The filter is comprised of a basic linear combiner formed with a nondestructively tapped CCD analog delay line and electrically reprogrammable MOS analog conductances as the tap weights. To demonstrate the feasibility of adaptive analog signal processing, a 2-tap weight CCD adaptive filter is described and experimental results presented.

Charge-coupled device (CCD) adaptive discrete analog signal processing

A CCD adaptive signal processor is described which uses a so-called "clipped-data" least mean square (LMS) error algorithm to optimize the selection of tap weights in a CCD filter. A detailed description of a 16-tap monolithic silicon CCD analog adaptive filter is also presented. The filter is comprised of a basic linear combiner formed with a nondestructively tapped CCD analog delay line and electrically reprogrammable MOS analog conductances as the tap weights. Two methods of varying the analog conductance are discussed: 1) variable V GS with fixed threshold voltage V T and 2) variable V T with fixed V GS . The former is performed with a CCD bidirectional charge control weight adjustment, whereas the latter is accomplished with MNOS memory transistors. To demonstrate the feasibility of adaptive analog signal processing, a 2-tap weight CCD adaptive filter is described and experimental results presented. Applications include optimum filtering, prediction, noise cancellation, and system modeling.

D.R. Lampe

Papers

Characterization of surface channel CCD image arrays at low light levels

Charge-coupled device (CCD) adaptive discrete analog signal processing

Charge-Coupled Device (CCD) Adaptive Discrete Analog Signal Processing