We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

Methods of Forming Strained-Semiconductor-on-Insulator Device Structures

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Semiconductor structure and method of manufacture

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

State of the Art and Future Perspectives in Advanced CMOS Technology.

A near field transducer includes gold and at least one dopant. The dopant can include at least one of: Cu, Rh, Ru, Ag, Ta, Cr, Al, Zr, V, Pd, Ir, Co, W, Ti, Mg, Fe, or Mo. The dopant concentration may be in a range from 0.5% and 30%. The dopant can be a nanoparticle oxide of V, Zr, Mg, Ca, Al, Ti, Si, Ce, Y, Ta, W, or Th, or a nitride of Ta, Al, Ti, Si, In, Fe, Zr, Cu, W or B.

Hamr nft materials with improved thermal stability

Ultra shallow junctions <500 /spl Aring/ with steep profiles <8 nm/decade are required for device technologies /spl les/0.13 /spl mu/m as outlined by the recent ITRS Roadmap. For a p/sup +//n junction such profiles can be obtained using sub-keV B ion implantation since both the projected range and more importantly the transient enhanced diffusion are significantly reduced at lower energies. State-of-the-art high current implanters utilize a deceleration mode typically for sub 1 keV implantation in order to increase the beam current and production wafer throughput. Such a mode contains a very low level of energy contamination. This level is measured for sub keV B implants in the Quantum Leap and factors affecting the level of contamination are studied. Spike and soak annealing reduces the effect of the energy contamination on junction profile and depth. The effect of energy contamination on device performance such as L/sub eff/, VT and I/sub DSAT/ is simulated using ISE TCAD.

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Junction profiles of sub keV ion implantation for deep sub-quarter micron devices

Reducing channeling of B implants and transient enhanced diffusion (TED) is very critical for the formation of ultra shallow junctions required for deep sub-micron devices. As the ion energy required for junction formation is reduced (<5 keV) due to device shrinking, the use of high tilt angle (typically 7-10 deg) becomes ineffective in suppressing channeling. The formation of a thin amorphous layer close to the surface prior to B implant has shown to be very efficient in eliminating channeling. Such layers can be formed using a Ge/sup +/ implant, and the thickness of the amorphous layers can be varied with Ge/sup +/ ion energy and dose. In addition if optimized, Ge/sup +/ pre-amorphization implants (PAI) can also minimize the TED of B by reducing the concentration of point defects generated by B implants. However, a Ge PAI itself introduces point defects and can result in TED with sub keV B implants. This paper explores the limits and optimized conditions of Ge PAI prior to low energy B implants (=1 keV) for the formation of junctions for deep sub-quarter micron devices.

Exploring the limits of pre-amorphization implants on controlling channeling and diffusion of low energy B implants and ultra shallow junction formation

A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate ( 211 ) overlying a semiconductor layer ( 203 ), and having at least one spacer structure ( 213 ) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion ( 215 ) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant ( 253, 254 ).

Method to improve source/drain parasitics in vertical devices

Predetermined regions of a transistor are activated using a buried energy absorbing layer. The buried energy absorbing layer is under a semiconductor layer, in which a transistor is being formed. Amorphous regions are formed within the semiconductor layer on either side of a control electrode and a gate dielectric. An energy source with a wavelength that is not absorbed by the amorphous regions or the control electrode is applied to the transistor and absorbed by the energy absorbing layer. The energy absorbing layer transfers the energy into heat, which is at a temperature greater than or equal to the melting temperature of the amorphous regions and less than the melting temperature of the semiconductor layer. Due to the heat, the amorphous regions melt and recrystallize, thereby becoming electrically active. However, the control electrode does not melt.

Method of forming a semiconductor device having an energy absorbing layer and structure thereof

Amorphous layers formed with Ge implantation into Si over a range of energy (5 to 70 keV) and dose (0.5 to 3/spl times/10/sup 15//cm/sup 2/) were characterized using carrier illumination (CI), variable angle spectroscopic ellipsometry (VASE), and cross-sectional transmission electron microscopy (XTEM). The CI signal varies lineariy with XTEM depth to 860 /spl Aring/. The VASE response is monotonic, and can be linearized with additional calibration. Both methods are sensitive to amorphous layer depth and exhibit no dose sensitivity. CI is additionally sensitive to depth differences between 0/spl deg/ to 7/spl deg/ implant angles.

D. Sing

Papers

Junction profiles of sub keV ion implantation for deep sub-quarter micron devices

Exploring the limits of pre-amorphization implants on controlling channeling and diffusion of low energy B implants and ultra shallow junction formation

Method to improve source/drain parasitics in vertical devices

Method of forming a semiconductor device having an energy absorbing layer and structure thereof

In-line characterization of preamorphous implants (PAI)