General trends in integrated circuit technology toward smaller device dimensions, lower thermal budgets, and simplified processing steps present severe physical and engineering challenges to ion implantation. These challenges, together with the need for physically based models at exceedingly small dimensions, are leading to a new level of understanding of fundamental defect science in Si. In this article, we review the current status and future trends in ion implantation of Si at low and high energies with particular emphasis on areas where recent advances have been made and where further understanding is needed. Particularly interesting are the emerging approaches to defect and dopant distribution modeling, transient enhanced diffusion, high energy implantation and defect accumulation, and metal impurity gettering. Developments in the use of ion beams for analysis indicate much progress has been made in one-dimensional analysis, but that severe challenges for two-dimensional characterization remain. The ...

Ion beams in silicon processing and characterization

Methods of Forming Strained-Semiconductor-on-Insulator Device Structures

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

State of the Art and Future Perspectives in Advanced CMOS Technology.

A near field transducer includes gold and at least one dopant. The dopant can include at least one of: Cu, Rh, Ru, Ag, Ta, Cr, Al, Zr, V, Pd, Ir, Co, W, Ti, Mg, Fe, or Mo. The dopant concentration may be in a range from 0.5% and 30%. The dopant can be a nanoparticle oxide of V, Zr, Mg, Ca, Al, Ti, Si, Ce, Y, Ta, W, or Th, or a nitride of Ta, Al, Ti, Si, In, Fe, Zr, Cu, W or B.

Hamr nft materials with improved thermal stability

The present invention provides methods for fabricating semiconductor structures and devices, particularly ultra-shallow doped semiconductor structures exhibiting low electrical resistance. Methods of the present invention use modification of the composition of semiconductor surfaces to allow fabrication of a doped semiconductor structure having a selected dopant concentration depth profile, which provides useful junctions and other device components in microelectronic and nanoelectronic devices, such as transistors in high density integrated circuits. Surface modification in the present invention also allows for control of the concentration and depth profile of defects, such as interstitials and vacancies, in undersaturated semiconductor materials.

Methods for controlling dopant concentration and activation in semiconductor structures

Ultra shallow junctions <500 /spl Aring/ with steep profiles <8 nm/decade are required for device technologies /spl les/0.13 /spl mu/m as outlined by the recent ITRS Roadmap. For a p/sup +//n junction such profiles can be obtained using sub-keV B ion implantation since both the projected range and more importantly the transient enhanced diffusion are significantly reduced at lower energies. State-of-the-art high current implanters utilize a deceleration mode typically for sub 1 keV implantation in order to increase the beam current and production wafer throughput. Such a mode contains a very low level of energy contamination. This level is measured for sub keV B implants in the Quantum Leap and factors affecting the level of contamination are studied. Spike and soak annealing reduces the effect of the energy contamination on junction profile and depth. The effect of energy contamination on device performance such as L/sub eff/, VT and I/sub DSAT/ is simulated using ISE TCAD.

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Junction profiles of sub keV ion implantation for deep sub-quarter micron devices

Compound implants using Si and F pre-implants with B and BF2 doping implants are investigated for B and F diffusion effects and residual defect levels. Physical methods (RBS, SIMS, SRP) are combined with optical scanning and depth profiling techniques (TW, PAD, Raman) to investigate the insights to be gained from use of a fuller set of characterization tools for defect engineering.

Defect engineering of p+-junctions by multiple-species ion implantation

Reducing channeling of B implants and transient enhanced diffusion (TED) is very critical for the formation of ultra shallow junctions required for deep sub-micron devices. As the ion energy required for junction formation is reduced (<5 keV) due to device shrinking, the use of high tilt angle (typically 7-10 deg) becomes ineffective in suppressing channeling. The formation of a thin amorphous layer close to the surface prior to B implant has shown to be very efficient in eliminating channeling. Such layers can be formed using a Ge/sup +/ implant, and the thickness of the amorphous layers can be varied with Ge/sup +/ ion energy and dose. In addition if optimized, Ge/sup +/ pre-amorphization implants (PAI) can also minimize the TED of B by reducing the concentration of point defects generated by B implants. However, a Ge PAI itself introduces point defects and can result in TED with sub keV B implants. This paper explores the limits and optimized conditions of Ge PAI prior to low energy B implants (=1 keV) for the formation of junctions for deep sub-quarter micron devices.

Exploring the limits of pre-amorphization implants on controlling channeling and diffusion of low energy B implants and ultra shallow junction formation

Modeling of ULSI ion implantation processing poses a complex set of challenges for efficient description of physical processes. Accuracy requirements for range and damage profiles and the need for advances in modeling of defect-enhanced diffusion and dopant activation of Si are rapidly increasing. The overriding requirement is the need to incorporate accurate physical models into efficient descriptions of 3-dimensional device structures.

Process simulation challenges for ULSI devices: A users perspective

Wafer charging effects in an Applied Materials 9500 implanter were studied for high current As and BF2 implants with EEPROM-based sense and measurement devices (CHARM(R)-2) and transistor structures (SPIDER). The operational modes of the implanter were deliberately driven non-optimal states in order 60 test the sensitivity of the wafer-level monitors. Good correlation was found between data from the CHARM and SPIDER monitors as well as from machine-based indicators, such as the wheel current. A broad and stable operating window was seen for operation under normal conditions.

L. Larson

Papers

Junction profiles of sub keV ion implantation for deep sub-quarter micron devices

Defect engineering of p+-junctions by multiple-species ion implantation

Exploring the limits of pre-amorphization implants on controlling channeling and diffusion of low energy B implants and ultra shallow junction formation

Process simulation challenges for ULSI devices: A users perspective

A study of wafer charging with CHARM and SPIDER monitors