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William J. Taylor
Researcher at Motorola
Publications - 30
Citations - 751
William J. Taylor is an academic researcher from Motorola. The author has contributed to research in topics: Gate dielectric & Layer (electronics). The author has an hindex of 13, co-authored 30 publications receiving 748 citations. Previous affiliations of William J. Taylor include Freescale Semiconductor & GlobalFoundries.
Papers
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Journal ArticleDOI
Fermi-level pinning at the polysilicon/metal-oxide interface-Part II
Christopher C. Hobbs,L. R. C. Fonseca,A. Knizhnik,V. Dhandapani,S. Samavedam,William J. Taylor,J. M. Grant,L. Dip,D. Triyoso,Rama I. Hegde,David C. Gilmer,R. Garcia,D. Roan,M.L. Lovejoy,Raghaw S. Rai,E. A. Hebert,Hsing-Huang Tseng,S.G.H. Anderson,Bruce E. White,Philip J. Tobin +19 more
TL;DR: In this article, it was shown that Fermi-pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices.
Patent
Method for forming a semiconductor device
TL;DR: In this article, the capacitance is inlaid in a cavity formed in the semiconductor substrate and part of a high density memory and a top electrode is then formed over the dielectric layer to isolate the bottom electrode from the top electrode preventing shorting and leakage currents.
Proceedings ArticleDOI
Dual-metal gate CMOS with HfO 2 gate dielectric
Srikanth B. Samavedam,L.B. La,James Nelson Smith,S. Dakshina-Murthy,E. Luckowski,J. Schaeffer,M. Zavala,Ryan Martin,V. Dhandapani,D. Triyoso,H.-H. Tseng,Philip J. Tobin,David C. Gilmer,Christopher C. Hobbs,William J. Taylor,J. M. Grant,Rama I. Hegde,J. Mogab,C. Thomas,P. Abramowitz,M. Moosa,J. Conner,Jack Jiang,V. Arunachalarn,Michael A. Sadd,Bich-Yen Nguyen,Bruce E. White +26 more
TL;DR: In this paper, a dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes was reported.
Patent
Transistor having a high K dielectric and short gate length and method therefor
TL;DR: In this article, the source/drains extensions (28 and 30) are minimized to extend substantially in alignment with the edge of gate dielectric (24), which results in reduced capacitance between the gate and source/drain extensions.
Patent
Method for forming a semiconductor device with an opening in a dielectric layer
Bich-Yen Nguyen,William J. Taylor,Philip J. Tobin,David L. O'Meara,Percy V. Gilbert,Yeong-Jyh Tom Lii,Victor Wang +6 more
TL;DR: In this paper, a method for forming a semiconductor device having an isolation region is disclosed, in which a dielectric layer is deposited and etched to form isolation regions ( 102, 605 ) having top portions that are narrower than their bottom portions, thereby a tapered isolation region was formed.