Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing t...

Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

Due to the enormous advances made in semiconductor technology over the last few years, high integration densities with moderate costs are achievable even in the millimeter-wave (mm-wave) range and beyond, which encourage the development of imaging systems with a high number of channels. The mm-wave range lies between 30 and 300 GHz, with corresponding wavelengths between 10 and 1 mm. While imaging objects with signals of a few millimeters in wavelength, many optically opaque objects appear transparent, making mm-wave imaging attractive for a wide variety of commercial and scientific applications like nondestructive testing (NDT), material characterization, security scanning, and medical screening. The spatial resolution in lateral and range directions as well as the image dynamic range offered by an imaging system are considered the main measures of performance. With the availability of more channels combined with the powerful digital signal processing (DSP) capabilities of modern computers, the performance of mm-wave imaging systems is advancing rapidly.

Advanced Microwave Imaging

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

This work presents a highly integrated 57–64 GHz 4-channel receiver 2-channel transmitter chip targeting short range sensing and large bandwidth communications. The chip is housed in an embedded wafer level ball grid array package. The package includes 6 integrated patch antennas realized with a metal redistribution layer. The receiver patch antennas have a combined antenna gain of $\approx 10$ dBi while each transmitter antenna has a gain of $\approx ~6$ dBi. The chip features a wide tuning range integrated VCO with a measured phase noise lower than −80 dBc/Hz at 100 kHz offset. Each of the differential transmitter channels shows a measured output power of 2–5 dBm over the complete frequency range. In addition, one transmitter channel features a modulator that can be digitally programmed to operate in either radar or communication mode. Each of the receiver channels has a measured conversion gain of 19 dB, a single-sideband noise figure of less than 10 dB and an input referred 1 dB compression point of less than 10 dBm. With all channels turned on the chip consumes a current of 300 mA from a 3.3 V supply. The functionality of the chip is demonstrated for both sensing and short range wireless communications.

A Highly Integrated 60 GHz 6-Channel Transceiver With Antenna in Package for Smart Sensing and Short-Range Communications

An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.

Integrated circuit having memory array including ECC and column redundancy and method of operating same

We present a transceiver chipset consisting of a four channel receiver (Rx) and a single-channel transmitter (Tx) designed in a 200-GHz SiGe BiCMOS technology. Each Rx channel has a conversion gain of 19 dB with a typical single sideband noise figure of 10 dB at 1-MHz offset. The Tx includes two exclusively-enabled voltage-controlled oscillators on the same die to switch between two bands at 76-77 and 77-81 GHz. The phase noise is -97 dBc/Hz at 1-MHz offset. On-wafer, the output power is 2 × 13 dBm. At 3.3-V supply, the Rx chip draws 240 mA, while the Tx draws 530 mA. The power dissipation for the complete chipset is 2.5 W. The two chips are used as vehicles for a 77-GHz package test. The chips are packaged using the redistribution chip package technology. We compare on-wafer measurements with on-board results. The loss at the RF port due to the transition in the package results to be less than 1 dB at 77 GHz. The results demonstrate an excellent potential of the presented millimeter-wave package concept for millimeter-wave applications.

An RCP Packaged Transceiver Chipset for Automotive LRR and SRR Systems in SiGe BiCMOS Technology

The notion of a "potential well" for charge storage in the floating body of the "capacitorless" DRAM cell is shown to be inadequate and misleading. The basic operation of the floating-body MOSFET cell (FBC) is physically overviewed, with supportive numerical device simulations and analytical modeling. New insights are revealed, including identification of the intrinsic dynamic capacitors that actually store the body charge. Multiple roles of an accumulation layer that is needed in fully depleted FBCs are physically defined for the first time. Optimal FBC designs are implied

New Insights on “Capacitorless” Floating-Body DRAM Cells

A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed.

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

Novel, or nonclassical effects due to carrier distribution in double-gate (DG) CMOS devices (e.g., FinFETs) with undoped ultra-thin silicon bodies (UTBs) are analyzed and modeled. The classical analysis of gate–gate charge coupling and threshold voltage (Vt) of fully depleted SOI MOSFETs by Lim and Fossum [Lim H-K, Fossum JG. Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs. IEEE Trans Electron Dev 1983;ED-30(October):1244–51.] is generalized to account for bulk inversion in UTBs, carrier-energy quantization, and short-channel effects (SCEs). The generalized charge coupling model physically and generically characterizes Vt for arbitrary gate biases, and explains an enhanced coupling in independent-gate (IG) FinFETs associated with bulk inversion. The impact of the carrier distribution on SCEs is also discussed. The effect on Vt of sparse, random dopants in the UTB is shown to be insignificant. Finally, bulk inversion is noted to prevail in strong inversion, where its net effect on device performance is beneficial.

Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies

Relative values of on-state current in undoped-body double-gate (DG) and triple-gate (TG) FinFETs are examined via three-dimensional numerical device simulations. The simulation results reveal significant bulk inversion in the fin bodies, which limits the benefit of the third (top) gate in the TG FinFET and which negates the utility of the commonly defined effective gate width (W/sub eff/=2h/sub Si/+w/sub Si/). Even the concept of W/sub eff/ for the TG FinFET is invalidated, but the proper W/sub eff/ for the DG FinFET is defined. Physical insights attained from the simulations further solidify our notion, based previously on gate layout-area inefficiency, that the third gate is neither desirable nor beneficial.

Vishal P. Trivedi

Papers

An RCP Packaged Transceiver Chipset for Automotive LRR and SRR Systems in SiGe BiCMOS Technology

New Insights on “Capacitorless” Floating-Body DRAM Cells

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies

Bulk inversion in FinFETs and implied insights on effective gate width