Showing papers by "Darko Stefanovic published in 2003"

A deoxyribozyme-based molecular automaton

Abstract: We describe a molecular automaton, called MAYA, which encodes a version of the game of tic-tac-toe and interactively competes against a human opponent. The automaton is a Boolean network of deoxyribozymes that incorporates 23 molecular-scale logic gates and one constitutively active deoxyribozyme arrayed in nine wells (3x3) corresponding to the game board. To make a move, MAYA carries out an analysis of the input oligonucleotide keyed to a particular move by the human opponent and indicates a move by fluorescence signaling in a response well. The cycle of human player input and automaton response continues until there is a draw or a victory for the automaton. The automaton cannot be defeated because it implements a perfect strategy.

Randomized instruction set emulation to disrupt binary code injection attacks

Abstract: Binary code injection into an executing program is a common form of attack. Most current defenses against this form of attack use a 'guard all doors' strategy, trying to block the avenues by which execution can be diverted. We describe a complementary method of protection, which disrupts foreign code execution regardless of how the code is injected. A unique and private machine instruction set for each executing program would make it difficult for an outsider to design binary attack code against that program and impossible to use the same binary attack code against multiple machines. As a proof of concept, we describe a randomized instruction set emulator (RISE), based on the open-source Valgrind x86-to-x86 binary translator. The prototype disrupts binary code injection attacks against a program without requiring its recompilation, linking, or access to source code. The paper describes the RISE implementation and its limitations, gives evidence demonstrating that RISE defeats common attacks, considers how the dense x86 instruction set affects the method, and discusses potential extensions of the idea.

Deoxyribozyme-based half-adder.

Abstract: We have constructed a solution-phase array of three deoxyribozyme-based logic gates that behaves as a half-adder. Two deoxyribozymes mimic i1ANDNOTi2 and i2ANDNOTi1 gates that cleave a fluorogenic substrate, reporting through an increase in fluorescence emission at 570 nm. The third deoxyribozyme mimics an i1ANDi2 gate and cleaves the other fluorogenic substrate, reporting through an increase in fluorescence emission at 520 nm. Together, this system represents the first example of a decision-making enzymatic network with two inputs and two outputs. Similar systems could be applied to control autonomous therapeutic and diagnostic devices.

Implicit-OR tiling of deoxyribozymes: Construction of molecular scale OR, NAND, and four-input logic gates *

Abstract: We recently reported the first complete set of molecular-scale logic gates based on deoxyribozymes. Here we report how we tile these logic gates and construct new logic elements: OR, NAND, and the first element with four inputs (i 1 Λi 5 )V(i 2 Λi 6 ). Tiling of logic gates was achieved through a common substrate used for core deoxyribozyme; degradation of this substrate defines the output. This kind of connection between logic gates is an implicit-OR tiling, because it suffices that one componenet of the network is active for the whole network to give an output of 1.

Model Checking Reconfigurable Processor Configurations for Safety Properties

Abstract: Reconfigurable processors pose unique problems for program safety because of their use of computational approaches that are difficult to integrate into traditional program analyses. The combination of proof-carrying code for verification of standard processor machine code and model-checking for array configurations is explored. This approach is shown to be useful in verifying safety properties including the synchronization of memory accesses by the reconfigurable array and memory access bounds checking.

Experiences Constructing a Lightweight SPARC Interpreter for a Dynamic Binary Translator

Abstract: : Dynamic binary translation is an important area for compiler research, because additional information available at runtime can substantially improve the effectiveness of optimizations. The difficulty lies in creating a system capable of gathering runtime information without slowing down the running executable. Several such systems have been created "Dynamo, DynamoRIO, FX!32, etc.", but their use presents several problems to the researcher. They are either closed or proprietary, and are often tied to a very specific platform. In this paper we discuss the design of a new, open, cross-platform dynamic binary translation system, SIND. Specifically we discuss the design in general terms, and then focus on the specific implementation of a lightweight interpreter for the SPARC architecture. We explore the many issues involved in building a self-bootstrapping efficient interpreter.

Model checking reconfigurable processor configurations for safety properties

Abstract: Reconfigurable processors pose unique problems for program safety because of their use of computational approaches that are difficult to integrate into traditional program analyses The combination of proof-carrying code for verification of standard processor machine code and model-checking for array configurations is explored This approach is shown to be useful in verifying safety properties including the synchronization of memory accesses by the reconfigurable array and memory access bounds checking