Showing papers by "David Esseni published in 2000"

Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs

Abstract: Electron and hole effective mobilities of ultra-thin SOI N- and P-MOSFETs have been measured at different temperatures using a special test structure able to circumvent parasitic resistance effects. At large inversion densities (N/sub inv/) ultra-thin SOI mobility can be higher than in heavily doped bulk MOS due a lower effective field and it is largely insensitive to silicon thickness (T/sub SI/). However, at small Ni/sub inv/ the mobility is clearly reduced for decreasing T/sub SI/. The effective mobility data are used to study the implications for ultra-short MOS transistor performance at device simulation level.

Trading-off programming speed and current absorption in flash memories with the ramped-gate programming technique

Abstract: This work studies the trade-off between programming speed and current absorption in flash EEPROM memories that can be achieved using a ramped-gate programming (RGP) method. The writing parallelism as a function of the programming speed is discussed and it is shown how the flexibility of the RGP scheme can be effectively used to meet very different programming requirements. In particular, the results of this paper address two significant applications: a highly parallel (2 K cells) soft-programming procedure able to remarkably tighten erased V/sub T/ distribution and a multilevel, high bandwidth (1 Mbytes/s) programming operation. For both applications, the most relevant issues for a practical use are discussed, such as the choice of drain and substrate voltages in relation to current absorption, the statistical distribution of programmed threshold voltages, and the endurance characteristics.

Injection efficiency of CHISEL gate currents in short MOS devices: physical mechanisms, device implications, and sensitivity to technological parameters

Abstract: This paper analyzes MOSFET gate currents in the so-called channel initiated secondary electron injection regime (CHISEL). A Monte Carlo model of the phenomenon is validated and then extensively used to explore CHISEL scaling laws. Results indicate that, compared to conventional channel hot electron injection (CHE), CHISEL exhibits a weaker dependence on channel length and a larger sensitivity to short channel effects. These results are confirmed experimentally and exhaustively explained with the help of simulations; furthermore, some of their possible detrimental consequences on the programming efficiency of CHISEL based flash cells are analyzed. Finally, the impact of channel doping, oxide thickness, and junction depth on CHISEL efficiency has been explored, and guidelines to maintain high injection efficiency in short devices are derived.

Substrate enhanced degradation of CMOS devices

Abstract: This paper investigates hot carrier induced nMOS and pMOS degradation in the presence of a substrate bias and compares the results with those of the conventional Channel Hot Carrier (CHC) regime Stress experiments and detailed characterizations (including spatial profiling of the damage) were carried out on state of the art n/sup +/-poly n-MOSFETs and p/sup +/-poly p-MOSFETs Results reveal that upon application of a substrate bias degradation becomes faster and more distributed towards the channel than in the channel hot carrier regime

Deuterium effect on interface states and SILC generation in CHE stress conditions: A comparative study

Abstract: This paper investigates the generation of interface states (N/sub it/) and stress induced leakage current (SILC) in the stress regime of channel hot electrons (CHE) and the possible beneficial effect of deuterium annealing. Our results show that no isotope effect is observed on SILC even when a large isotope effect is simultaneously observed on N/sub it/. The generation of SILC seems to be always correlated to hot holes injection (HHI) whereas two different generation mechanisms for N/sub it/ can be identified.