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David Nin-Kou Wang

Researcher at Applied Materials

Publications -  42
Citations -  3930

David Nin-Kou Wang is an academic researcher from Applied Materials. The author has contributed to research in topics: Wafer & Layer (electronics). The author has an hindex of 25, co-authored 42 publications receiving 3930 citations.

Papers
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Patent

Multiple chamber integrated process system

TL;DR: In this paper, an integrated modular multiple chamber vacuum processing system is described, which includes a load lock, may include an external cassette elevator and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load-lock chamber.
Patent

Reactor chamber self-cleaning process

TL;DR: In this paper, a two-step continuous etch sequence is used in which the first step uses relatively high pressure, close electrode spacing and fluorocarbon gas chemistry for etching the electodes locally and the second step uses a relatively lower pressure, farther electrode spacing, and fluorinated gas chemistry to etch throughout the chamber and exhaust system.
Patent

CVD of silicon oxide using TEOS decomposition and in-situ planarization process

TL;DR: In this paper, a high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD and plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.
Patent

Magnetic field-enhanced plasma etch reactor

TL;DR: A magnetic field enhanced single wafer plasma etch reactor is described in this article, which includes an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting cathode; and a unitary wafer exchange mechanism comprising wafer lift pins which extend through the pedestal and a wafer clamp ring.
Patent

Process for PECVD of silicon oxide using TEOS decomposition

TL;DR: In this article, a high pressure, high throughput, single wafer, semiconductor processing reactor is described which is capable of thermal CVD, plasma-enhanced CVD and plasma assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.