Debiprasanna Sahoo

TL;DR: This work proposes a fuzzy logic-based fairness control mechanism that characterizes the degree of flow intensity of a workload and assigns priorities to the workloads and observes that the proposed mechanism improves the fairness, weighted speedup, and harmonic speedup of SSD by 29.84, 11.24, and 24.90% on average over state of the art.

TL;DR: A realistic model for determining the wake-up time of registers from various under-volting and power gating modes is developed and a hybrid energy saving technique where a combination of power-gating and under-Volting can be used to save optimum energy depending on the idle period of the registers with a negligible performance penalty is proposed.

TL;DR: The authors have developed the formal model of a truncated simulator which preserves the behaviour of each agent and agent-interaction and this formal model is used as a reference for implementing MSimDRAM, the final simulator.

TL;DR: This research selects a common variant of DRAM cache and builds a formal model of its controller in terms of interacting state machines; it verify safety, liveness, and timing properties of this variant using model checking and demonstrates how the formal models and the associated properties of other variants of DCCs can be derived from the base model in a systematic way.

TL;DR: CAMO is presented, a novel cache memory organization for GPGPUs which addresses the limitations of pinned memory technique and GPUdmm and uses ATCache, a CPU based DRAM cache tag management technique.