Derek Chou

TL;DR: In this article, the authors present a 2-kW, 60-Hz, 450-V -to-240-V power inverter, designed and tested subject to the specifications of the Google/IEEE Little Box Challenge, which achieves a high power density of 216 W/in $3$ and a peak overall efficiency of 97.6%, while meeting the constraints including input current ripple, load transient, thermal, and FCC Class B EMC specifications.

TL;DR: In this article, the authors present a 2 kW, 60 Hz, 450 VDC to 240 VRMS power inverter, designed and tested subject to the specifications of the Google/IEEE Little Box Challenge.

TL;DR: A power factor correction (PFC) front end based on a seven-level flying capacitor multilevel (FCML) boost converter that features the use of low-voltage-rated transistors, reduced voltage stress, and high effective switching frequency on the filter inductor to significantly improve the power density of the PFC front end compared to conventional solutions.

TL;DR: The design and implementation of a high power density Level II charger converting between 400 VDC and 240 VAC is discussed, utilizing two interleaved flying-capacitor multilevel converter stages combined with a full H-bridge unfolder or active rectifier with the goal of high efficiency and power density.

TL;DR: This prototype is the first successful demonstration of a 7-level flying capacitor multilevel boost topology as an AC-DC converter with fully implemented digital PFC control and self-powered start-up from a universal AC input.