This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

An intermediate substrate includes a handle substrate bonded to a thin layer suitable for epitaxial growth of a compound semiconductor layer, such as a III-nitride semiconductor layer. The handle substrate may be a metal or metal alloy substrate, such as a molybdenum or molybdenum alloy substrate, while the thin layer may be a sapphire layer. A method of making the intermediate substrate includes forming a weak interface in the source substrate, bonding the source substrate to the handle substrate, and exfoliating the thin layer from the source substrate such that the thin layer remains bonded to the handle substrate.

Bonded intermediate substrate and method of making same

A multi-junction solar cell includes an active silicon subcell, a first non-silicon subcell bonded to a first side of the active silicon subcell, and a second non-silicon subcell bonded to a second side of the active silicon subcell. This and other solar cells may be formed by bonding and layer transfer.

Multi-junction solar cells and methods of making same using layer transfer and bonding techniques

A method of making a virtual substrate includes providing a donor substrate comprising a single crystal donor layer of a first material over a support substrate, wherein the first material comprises a ternary, quaternary or penternary semiconductor material or a material which is not available in bulk form, bonding the donor substrate to a handle substrate, and separating the donor substrate from the handle substrate such that a single crystal film of the first material remains bonded to the handle substrate.

High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials

GaN electronics constitutes a revolutionary technology with power handling capabilities that amply exceed those of Si and other semiconductors in many applications. RF, microwave, and millimeter-wave GaN-based power amplifiers are now deployed in commercial communications, radar, and sensing systems. GaN power transistors for electrical power management are also starting to reach the marketplace. From the dawn of this technology, inadequate transistor stability and reliability have represented stumbling blocks preventing widespread commercial use of GaN electronics. Intense research has been devoted to addressing these issues, and great progress has taken place recently. This article reviews some of the most interesting and significant stability and reliability issues that have plagued GaN power field-effect transistors for RF and power management applications.

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Stability and Reliability of Lateral GaN Power Field-Effect Transistors

SiGe-free strained Si on insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced capacitance and improved scalability of thin film silicon on insulator (SOI). We demonstrate fabrication of 20% Ge equivalent strain level SSOI substrates with Si thicknesses of 100 and 400 A by hydrogen-induced layer transfer of strained Si layers from high quality graded SiGe virtual substrates. The substrate properties are excellent: wafer scale strained Si film thickness uniformities are better than 8%, strained Si surface roughnesses are better than 0.5 nm RMS, and robust tensile strain levels are maintained during anneals as long as 80 min at 1100 °C. Fully depleted n-MOSFET electrical results show that biaxial tensile strain, and hence enhanced mobility, is fully maintained in the 400 A 20% SSOI films through the substrate and device fabrication processes, even after a generous FET fabrication thermal budget. Long channel devices exhibit nearly ideal subthreshold slopes of 66 mV/decade and exhibit 112% electron mobility enhancements at Ninv=1×1013 cm−2, identical to devices on bulk strained Si substrates. Furthermore, a photoemission microscopy study was used to confirm that the useable SSOI layer thickness significantly exceeds the critical thickness for fabrication of bulk strained Si FETs without deleterious leakage current effects. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator is an ideal platform for future generations of Si-based microelectronics.

Strained Si on insulator technology: from materials to devices

We have fabricated self-aligned tight-pitch InGaAs Quantum-well MOSFETs (QW-MOSFETs) with scaled channel thickness (t c ) and metal contact length (L c ) by a novel fabrication process that features precise dimensional control. Impact of t c scaling on transport, resistance and short channel effects (SCE) has been studied. A thick channel is favorable for transport, and a mobility of 8800 cm2/V·s is obtained with t c =11 nm at N s =2.6×1012 cm−2. Also, a record g m,max of 3.1 mS/µm and R on of 190 Ω·µm are obtained in MOSFETs with t c =9 nm and gate length L g =80 nm. In contrast, a thin channel is beneficial for SCE control. In a device with t c =4 nm and L g =80 nm, S is 111 mV/dec at V ds = 0.5 V. For the first time, working front-end device structures with 40 nm long contacts and gate-to-gate pitch of 150 nm are demonstrated. A new method to study the resistance properties of nanoscale contacts is proposed. We derive a specific contact resistivity between the Mo contact metal and the n+ InGaAs cap of ρ=(8±2)×10−9 Ω·cm2. We also infer a metal-to-channel resistance of 70 Ω·µm for 40 nm long contacts.

Novel intrinsic and extrinsic engineering for high-performance high-density self-aligned InGaAs MOSFETs: Precise channel thickness control and sub-40-nm metal contacts

In this work, we have developed two different fabrication processes for relaxed Si1xGex-on-insulator (SGOI) substrates: (1) SGOI fabrication by etch-back approach, and (2) by “smart-cut” approach utilizing hydrogen implantation Etch-back approach produces SGOI substrate with less defects in SiGe film, but the SiGe film uniformity is inferior “Smart-cut” approach has better control on the SiGe film thickness and uniformity, and is applicable t o wider Ge content range of the SiGe film We have also fabricated strained-Si n-MOSFET’s on SGOI substrates, in which epitaxial regrowth was used to produce the surface strained Si layer on relaxed SGOI substrate, followed by large-area nMOSFET’s fabrication on this structure The measured electron mobility shows significant enhancement (17 times) over both the universal mobility and that of co-processed bulk-Si MOSFET’s This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si1-xGex layer

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SiGe-On-Insulator (SGOI) Technology and MOSFET Fabrication

We report, for the first time, a prominent but fully reversible enhancement in transconductance after applying positive gate stress to self-aligned InGaAs MOSFETs. We attribute this to electric-field-induced migration of fluorine ions (F−) introduced during the RIE gate recess process. F− is known to passivate Si donors in InAlAs. In our device structure, an n-InAlAs ledge facilitates the link from the contacts to the intrinsic device. We use secondary ion mass spectroscopy (SIMS) to independently confirm that our process leads to F pile up at the n-InAlAs layer. Transmission line model (TLM) structures confirm F−-induced donor passivation. The understanding derived has lead us to redesign our InGaAs MOSFETs by eliminating n-InAlAs layers and instead use an n-InP ledge. The new device design not only exhibits greatly improved electrical stability but also record performance.

Electric-field induced F − migration in self-aligned InGaAs MOSFETs and mitigation

The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulatorsemiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO2 co-sputtered middle layer (i.e., lower Ge concentration), a higher charge storage capability was obtained than with devices with a thinner RTO layer, and the charge retention time was found to be less than in devices with a thicker RTO layer.

Dependence of nanocrystal formation and charge storage/retention performance of a tri-layer memory structure on germanium concentration and tunnel oxide thickness

Dimitri A. Antoniadis

Papers

Strained Si on insulator technology: from materials to devices

Novel intrinsic and extrinsic engineering for high-performance high-density self-aligned InGaAs MOSFETs: Precise channel thickness control and sub-40-nm metal contacts

SiGe-On-Insulator (SGOI) Technology and MOSFET Fabrication

Electric-field induced F − migration in self-aligned InGaAs MOSFETs and mitigation

Dependence of nanocrystal formation and charge storage/retention performance of a tri-layer memory structure on germanium concentration and tunnel oxide thickness