The past decade has seen rapid progress in research into high-performance Ge-on-Si photodetectors. Owing to their excellent optoelectronic properties, which include high responsivity from visible to near-infrared wavelengths, high bandwidths and compatibility with silicon complementary metal–oxide–semiconductor circuits, these devices can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and infrared imaging at low cost and low power consumption. This Review summarizes the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors. Owing to their excellent optoelectronic properties, Ge-on-Si photodetector can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and low-cost infrared imaging at low power consumption. This Review covers the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors.

High-performance Ge-on-Si photodetectors

This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

A detailed theoretical picture is given for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III–V channel metal-oxide-semiconductor field-effect transistors. For the technologically important in-plane biaxial and longitudinal uniaxial stress, changes in energy band splitting and warping, effective mass, and scattering are investigated by symmetry, tight-binding, and k⋅p methods. The results show both types of stress split the Si conduction band while only longitudinal uniaxial stress along ⟨110⟩ splits the Ge conduction band. The longitudinal uniaxial stress warps the conduction band in all semiconductors. The physics of the strain altered valence bands for Si, Ge, and III–V semiconductors are shown to be similar although the strain enhancement of hole mobility is largest for longitudinal uniaxial compression in ⟨110⟩ channel devices and channel materials with substantial differences between heavy and light hole masses such as Ge and GaAs. Furthermore, for all these materials,...

Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors

An intermediate substrate includes a handle substrate bonded to a thin layer suitable for epitaxial growth of a compound semiconductor layer, such as a III-nitride semiconductor layer. The handle substrate may be a metal or metal alloy substrate, such as a molybdenum or molybdenum alloy substrate, while the thin layer may be a sapphire layer. A method of making the intermediate substrate includes forming a weak interface in the source substrate, bonding the source substrate to the handle substrate, and exfoliating the thin layer from the source substrate such that the thin layer remains bonded to the handle substrate.

Bonded intermediate substrate and method of making same

Hybrid silicon lasers based on bonded III–V layers on silicon are currently the best contenders for on-chip lasers for silicon photonics. On-chip silicon light sources are highly desired for use as electrical-to-optical converters in silicon-based photonics. Zhiping Zhou and Bing Yin of Peking University in China and Jurgen Michel of Massachusetts Institute of Technology assess the three main contenders for such light sources: erbium-based light sources, germanium-on-silicon lasers and III-V-based silicon lasers. They consider operating wavelength, pumping conditions, power consumption, thermal stability and fabrication process. The scientists regard the power efficiencies of electrically pumped erbium-based lasers as being too low and the threshold currents of germanium lasers as being too high. They conclude that III–V quantum dot lasers monolithically grown on silicon show the most promise for realizing on-chip lasers.

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On-chip light sources for silicon photonics

Surface channel strained Si metal–oxide–semiconductor field-effect transistors (MOSFETs) are a leading contender for future high performance complementary metal–oxide–semiconductor (CMOS) applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n- and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n- and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFE...

Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates

We show that pure Ge grown selectively on SiO2/Si substrates in 100 nm holes is highly perfect at the top surface compared to conventional Ge lattice-mismatched growth on planar Si substrates. This result is achieved through a combination of interferometric lithography SiO2/Si substrate patterning and ultrahigh vacuum chemical vapor deposition Ge selective epitaxial growth. This “epitaxial necking,” in which threading dislocations are blocked at oxide sidewalls, shows promise for dislocation filtering and the fabrication of low-defect density Ge on Si. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in lattice-mismatched systems.

High quality Ge on Si by epitaxial necking

This paper studies the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates. NMOSFETs were fabricated on strained silicon substrates with various strained silicon thicknesses, both above and below the strained silicon critical thickness. The low field electron mobility and subthreshold characteristics of the devices were measured. Low field electron mobility is increased by about 1.8 times on all wafers and is not significantly degraded on any of the samples, even for a strained silicon thickness far greater than the critical thickness. From the subthreshold characteristics, however, it is shown that the off-state leakage current is greatly increased for the devices on the wafers with a strained silicon thickness that exceeds the critical thickness. The mechanism of the leakage was examined by using photon emission microscopy. Strong evidence is shown that the leakage mechanism is source/drain electrical shorting caused by enhanced dopant diffusion near misfit dislocations.

https://iopscience.iop.org/article/10.1088/0268-1242/19/1/L02/pdf

Film thickness constraints for manufacturable strained silicon CMOS

SiGe-free strained Si on insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced capacitance and improved scalability of thin film silicon on insulator (SOI). We demonstrate fabrication of 20% Ge equivalent strain level SSOI substrates with Si thicknesses of 100 and 400 A by hydrogen-induced layer transfer of strained Si layers from high quality graded SiGe virtual substrates. The substrate properties are excellent: wafer scale strained Si film thickness uniformities are better than 8%, strained Si surface roughnesses are better than 0.5 nm RMS, and robust tensile strain levels are maintained during anneals as long as 80 min at 1100 °C. Fully depleted n-MOSFET electrical results show that biaxial tensile strain, and hence enhanced mobility, is fully maintained in the 400 A 20% SSOI films through the substrate and device fabrication processes, even after a generous FET fabrication thermal budget. Long channel devices exhibit nearly ideal subthreshold slopes of 66 mV/decade and exhibit 112% electron mobility enhancements at Ninv=1×1013 cm−2, identical to devices on bulk strained Si substrates. Furthermore, a photoemission microscopy study was used to confirm that the useable SSOI layer thickness significantly exceeds the critical thickness for fabrication of bulk strained Si FETs without deleterious leakage current effects. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator is an ideal platform for future generations of Si-based microelectronics.

Strained Si on insulator technology: from materials to devices

Strained Ge p-channel heterostructures have been realized by hybrid-epitaxial growth. Strain-tuning Si0.4Ge0.6 virtual substrates were grown by ultra-high vacuum chemical vapour deposition and active layers were deposited by solid-source molecular beam epitaxy at low temperature. Following ex situ annealing, Hall effect measurements revealed a hole mobility of 1900 cm2 V−1 s−1 at 300 K (27 000 cm2 V−1 s−1 at 10 K), with a density of 1.8 × 1012 cm−2, giving a conductance in excess of current Ge heterostructures. Using a maximum-entropy mobility-spectrum analysis, 1.0 × 1012 cm−2 of these holes were found to have a mobility of 2700 cm2 V−1 s−1 at 300 K.

C. W. Leitz

Papers

Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates

High quality Ge on Si by epitaxial necking

Film thickness constraints for manufacturable strained silicon CMOS

Strained Si on insulator technology: from materials to devices

High conductance Ge p-channel heterostructures realized by hybrid epitaxial growth