1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A solution-processing method known as solution shearing is used to introduce lattice strain to organic semiconductors, thus improving charge carrier mobility. Solution-processed organic semiconductors show great promise for application in cheap and flexible electronic devices, but generally suffer from greatly reduced electronic performance — most notably charge-carrier mobilities — compared with their inorganic counterparts. Borrowing a trick from the inorganic semiconductor community, Giri et al. show how the introduction of strain into an organic semiconductor, through a simple solution-processing technique, modifies the molecular packing within the material and hence its electronic performance. For one material studied, the preparation of a strained structure is shown to more than double the charge-carrier mobility. Circuits based on organic semiconductors are being actively explored for flexible, transparent and low-cost electronic applications1,2,3,4,5. But to realize such applications, the charge carrier mobilities of solution-processed organic semiconductors must be improved. For inorganic semiconductors, a general method of increasing charge carrier mobility is to introduce strain within the crystal lattice6. Here we describe a solution-processing technique for organic semiconductors in which lattice strain is used to increase charge carrier mobilities by introducing greater electron orbital overlap between the component molecules. For organic semiconductors, the spacing between cofacially stacked, conjugated backbones (the π–π stacking distance) greatly influences electron orbital overlap and therefore mobility7. Using our method to incrementally introduce lattice strain, we alter the π–π stacking distance of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) from 3.33 A to 3.08 A. We believe that 3.08 A is the shortest π–π stacking distance that has been achieved in an organic semiconductor crystal lattice (although a π–π distance of 3.04 A has been achieved through intramolecular bonding8,9,10). The positive charge carrier (hole) mobility in TIPS-pentacene transistors increased from 0.8 cm2 V−1 s−1 for unstrained films to a high mobility of 4.6 cm2 V−1 s−1 for a strained film. Using solution processing to modify molecular packing through lattice strain should aid the development of high-performance, low-cost organic semiconducting devices.

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Tuning charge transport in solution-sheared organic semiconductors using lattice strain

This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

The piezoresistance effect of silicon1 has been widely used in mechanical sensors2,3,4, and is now being actively explored in order to improve the performance of silicon transistors5,6. In fact, strain engineering is now considered to be one of the most promising strategies for developing high-performance sub-10-nm silicon devices7. Interesting electromechanical properties have been observed in carbon nanotubes8,9. In this paper we report that Si nanowires possess an unusually large piezoresistance effect compared with bulk. For example, the longitudinal piezoresistance coefficient along the 〈111〉 direction increases with decreasing diameter for p-type Si nanowires, reaching as high as −3,550 × 10−11 Pa–1, in comparison with a bulk value of −94 × 10−11 Pa−1. Strain-induced carrier mobility change and surface modifications have been shown to have clear influence on piezoresistance coefficients. This giant piezoresistance effect in Si nanowires may have significant implications in nanowire-based flexible electronics, as well as in nanoelectromechanical systems.

/pdf/giant-piezoresistance-effect-in-silicon-nanowires-6auicc419y.pdf

Giant piezoresistance effect in silicon nanowires

The control of heat conduction through the manipulation of phonons as coherent waves in solids is of fundamental interest and could also be exploited in applications, but coherent heat conduction has not been experimentally confirmed. We report the experimental observation of coherent heat conduction through the use of finite-thickness superlattices with varying numbers of periods. The measured thermal conductivity increased linearly with increasing total superlattice thickness over a temperature range from 30 to 150 kelvin, which is consistent with a coherent phonon heat conduction process. First-principles and Green’s function–based simulations further support this coherent transport model. Accessing the coherent heat conduction regime opens a new venue for phonon engineering for an array of applications.

http://science.sciencemag.org/content/sci/338/6109/936.full.pdf

Coherent phonon heat conduction in superlattices.

Lattice-mismatched relaxed graded composition layers in the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems have recently been created with unprecedented high quality due to advances in understanding the impact of epitaxial growth conditions. The key process–property correlation is the impact of growth conditions on dislocation dynamics. In particular, the SiGe/Si system has recently been well explored experimentally, allowing the dislocation dynamic model to be tested. We show that the dislocation dynamics model is in general applicable to graded layers in any material system as long as dislocation flow is not impeded. In the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems, with moderately dislocated graded layers, these mechanisms can be absent under appropriate growth conditions. However, in all systems, threading dislocation impediments eventually occur under continued deformation through continued grading. The mechanism in SiGe/Si is related to the impediment of dislocation flow from the surface morphology and strain-fields from misfit dislocations. In the III–V systems, we observe that a planar defect, referred to here as branch defects, can form under a wide range of growth conditions, and these defects will lead to inhibited dislocation flow. The quantitative nature of these effects can be empirically modeled with the same dislocation dynamic model by incorporating a composition-dependent change in the effective strain experienced by threading dislocations during grading-induced deformation.

Dislocation dynamics in relaxed graded composition semiconductors

The effects of growth temperature, substrate offcut, and dislocation pileup formation on threading dislocation density (TDD) in compositionally graded SiGe buffers are explored. To investigate dislocation glide kinetics in these structures, a series of identical samples graded to 30% Ge were grown at temperatures between 650 and 900 °C on (001)-, (001) offcut 6° towards an in-plane 〈110〉-, and (001) offcut 6° towards an in-plane 〈100〉-oriented Si substrates. The field threading dislocation density (field TDD) in the on-axis samples varied exponentially with temperature, from 3.7×106 cm−2 at 650 °C to 9.3×104 cm−2 at 900 °C. The activation energy for dislocation glide in this series, calculated from the evolution of field TDD with growth temperature, was 1.38 eV, much lower than the expected value for this composition. This deviation indicates that strain accumulating during the grading process at low growth temperatures is forcing further dislocation nucleation, resulting in a deviation from pure glide-limited relaxation. The TDD of samples grown on offcut substrates exhibited a more complicated temperature dependence, likely because films grown on offcut substrates have an increased tendency towards saturation in dislocation reduction reactions at high temperature. Dislocation reduction processes were further explored by initiating compositional grading up to 15% Ge at 650 °C and continuing the grade to 30% Ge at 900 °C. The low temperature portion of this growth provided an excess concentration of threading dislocations which could subsequently be annihilated during the high temperature portion of the growth, enabling a comparison of reduction rates for different substrate offcuts. Combining these results with threading dislocation densities in a variety of other samples, a complete picture of strain relaxation kinetics in compositionally graded SiGe/Si emerges. Generally, strain relaxation in these structures is limited by dislocation glide, and threading dislocation densities are independent of final Ge content. However, we theorize that dislocation pileup formation inhibits the strain relaxation process and is therefore accompanied by a rise in field threading dislocation density. Based on these results, we now have a predictive model for TDD in compositionally graded SiGe/Si over a wide range of growth conditions.

Dislocation glide and blocking kinetics in compositionally graded SiGe/Si

Minority carrier lifetimes and interface recombination velocities for GaAs grown on a Si wafer using compositionally graded GeSi buffers have been investigated as a function of GaAs buffer thickness using monolayer-scale control of the GaAs/Ge interface nucleation during molecular beam epitaxy. The GaAs layers are free of antiphase domain disorder, with threading dislocation densities measured by etch pit density of 5×105–2×106 cm−2. Analysis indicates no degradation in either minority carrier lifetime or interface recombination velocity down to a GaAs buffer thickness of 0.1 μm. In fact, record high minority carrier lifetimes exceeding 10 ns have been obtained for GaAs on Si with a 0.1 μm GaAs buffer. Secondary ion mass spectroscopy reveals that cross diffusion of Ga, As, and Ge at the GaAs/Ge interface formed on the graded GeSi buffers are below detection limits in the interface region, indicating that polarity control of the GaAs/Ge interface formed on GeSi/Si substrates can be achieved.

Mayank T. Bulsara

Papers

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

Coherent phonon heat conduction in superlattices.

Dislocation dynamics in relaxed graded composition semiconductors

Dislocation glide and blocking kinetics in compositionally graded SiGe/Si

Impact of GaAs buffer thickness on electronic quality of GaAs grown on graded Ge/GeSi/Si substrates