All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

Nanowire transistors without junctions

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

Using intuitionistic fuzzy sets for fault-tree analysis on printed circuit board assembly

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

A stacked three-dimensional six transistor SRAM cell using a novel vertical slit field effect transistor with two independently controlled gates is proposed. A compact stacked 3D memory cell topology with a highly regular layout is presented and a significant memory cell area reduction can be achieved. Utilization of independent double gate transistors enhances the robustness for read and write operation. The trade-off for the use of independently controlled gates to increase the cell stability is discussed.

Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

This paper introduces a new device architecture, which can be shared by a variety of different types of transistors including a new 3D junctionless N-channel and P-channel vertical slit FET (VeSFET). VeSFETs have two symmetrical independent gates that provide many new circuit level opportunities e.g. in energy conservation domain, unavailable otherwise. The key feature of the new architecture is its extreme regularity, which promotes highly repetitive layouts, constructed with small number of massively replicated simple geometrical patterns vastly simplifying critical lithography steps. A single layer of VeSFETs is a canvas for Vertical Slit Transistor based Integrated Circuits (VeSTICs) [2,3]. This paper discusses the basic idea of vertical slit device architecture, the physics of VeSFETs, their key electrical properties in comparison with trigate FinFETs, and shows experimental characteristics of fabricated devices.

Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current ( ; 106). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

This paper extends the CMOS standard cells characterization methodology for defect based testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions - "Wired-AND" and "Wired-OR" are used. Examples of industrial standard cells characterization indicate that a single logic fault probability table is not sufficient. Separate tables for " Wired-AND " and " Wired-OR" conditions at the inputs are needed for full characterization and hierarchical test generation.

CMOS standard cells characterization for defect based testing

In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area.

Dominik Kasprowicz

Papers

Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration

Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

CMOS standard cells characterization for defect based testing

Is there always performance overhead for regular fabric