N
Nansheng Shen
Researcher at Agency for Science, Technology and Research
Publications - 16
Citations - 491
Nansheng Shen is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: Layer (electronics) & CMOS. The author has an hindex of 11, co-authored 16 publications receiving 453 citations.
Papers
More filters
Journal ArticleDOI
Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires
TL;DR: In this paper, a vertical silicon-nanowire (SiNW)-based tunneling field effect transistor (TFET) using CMOS-compatible technology was demonstrated, and the obtained 53 muA/mum I on can be further enhanced with heterostructures at the tunneling interface.
Proceedings Article
Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration
Wojciech Maly,Navab Singh,Zhixian Chen,Nansheng Shen,Xiang Li,Andrzej Pfitzner,Dominik Kasprowicz,Wieslaw Kuzmicz,Y-W. Lin,Malgorzata Marek-Sadowska +9 more
TL;DR: In this paper, a 3D junctionless N-channel and P-channel vertical slit FET (VeSFET) was introduced, which can be shared by a variety of different types of transistors.
Proceedings ArticleDOI
Highly compact 1T-1R architecture (4F 2 footprint) involving fully CMOS compatible vertical GAA nano-pillar transistors and oxide-based RRAM cells exhibiting excellent NVM properties and ultra-low power operation
X. P. Wang,Zheng Fang,Xiang Li,Bingyan Chen,Bin Gao,Jinfeng Kang,Zhixian Chen,A. Kamath,Nansheng Shen,Navab Singh,G. Q. Lo,Dim-Lee Kwong +11 more
TL;DR: In this article, a nano-meter-scaled 1T-1R nonvolatile memory (NVM) architecture comprising of RRAM cells built on vertical GAA nano-pillar transistors, either junction-less or junction-based, is systematically investigated.
Journal ArticleDOI
Multibit Programmable Flash Memory Realized on Vertical Si Nanowire Channel
TL;DR: In this paper, a programmable programmable vertical silicon nanowire (SiNW) SONOS memory using a top-down method was demonstrated, and the flash devices realized on highly scaled squarish SiNW down to 20 nm in diagonal showed much improved program/erase speed and window along with good retention and endurance characteristics as compared to the ones with large dimension.
Journal ArticleDOI
Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire
Xiang Li,Zhixian Chen,Nansheng Shen,Deblina Sarkar,Navab Singh,Kaustav Banerjee,Guo-Qiang Lo,Dim-Lee Kwong +7 more
TL;DR: In this article, the authors demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology.