Proceedings ArticleDOI
CMOS standard cells characterization for defect based testing
Witold A. Pleskacz,Dominik Kasprowicz,T. Oleszczak,Wieslaw Kuzmicz +3 more
- pp 384-392
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TLDR
This paper extends the CMOS standard cells characterization methodology for defect based testing to find the types of faults which may occur in a real IC, to determine their probabilities, and to finding the input test vectors which detect these faults.Abstract:
This paper extends the CMOS standard cells characterization methodology for defect based testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions - "Wired-AND" and "Wired-OR" are used. Examples of industrial standard cells characterization indicate that a single logic fault probability table is not sufficient. Separate tables for " Wired-AND " and " Wired-OR" conditions at the inputs are needed for full characterization and hierarchical test generation.read more
Citations
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Journal ArticleDOI
Low-cost testing of 5 GHz low noise amplifiers using new RF BIST circuit
Jee-Youl Ryu,Bruce Kim +1 more
TL;DR: A new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems is presented.
Journal ArticleDOI
DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits
TL;DR: A unique remote laboratory for studying CMOS physical defects that is meant to be used in advanced courses in the scope of microelectronic design and test and accessible over the Internet, thereby supporting distance learning and e-learning modes of training.
Proceedings ArticleDOI
A new BIST scheme for 5GHz low noise amplifiers
TL;DR: A new low-cost Built-In Self-Test (BIST) circuit for measuring gain, noise figure and input impedance of 5GHz low noise amplifier (LNA) is presented.
Journal ArticleDOI
Improvement of integrated circuit testing reliability by using the defect based approach
TL;DR: It is shown that a stuck-at-fault-optimized test-vector set may prove highly inefficient in detecting spot-defect-induced faults, and a few methods are discussed that make the DBT less time consuming.
Journal ArticleDOI
A new approach for built-in self-test of 4.5 to 5.5 GHz low-noise amplifiers
Jee-Youl Ryu,Seok-Ho Noh +1 more
TL;DR: This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs).
References
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Journal ArticleDOI
Inductive Fault Analysis of MOS Integrated Circuits
TL;DR: Given the layout of an IC, a fault model and a ranked fault list can be automatically generated which take into account the technology, layout, and process characteristics.
Journal ArticleDOI
Integrated circuit yield statistics
TL;DR: In this paper, the random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process, which allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing.
Journal ArticleDOI
Modeling of defects in integrated circuit photolithographic patterns
TL;DR: This paper shows how to calculate the critical areas and probability of failure for dense arrays of wiring and the results are used to determine the nature of the defect size distribution with electronic defect monitors.
Journal ArticleDOI
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
TL;DR: Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.
Journal ArticleDOI
Yield estimation model for VLSI artwork evaluation
Wojciech Maly,J. Deszczka +1 more
TL;DR: In this article, a model which describes limitations of a manufacturing yield in terms of an IC artwork and a lithography characterisation is proposed, where density and distribution of diameters of defects present in the mask, as well as line width fluctuations, are taken into account.