International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges.

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Status and Prospects of ZnO-Based Resistive Switching Memory Devices

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.

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FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Analysis of cooling load on commercial building in UAE climate using building integrated photovoltaic façade system

The dark current–voltage of the Au/n+(a-Si:H)/n(SiGe)/p(c-Si)/Ag heterojunction structure have been investigated in order to determinate the electrical conduction mechanisms. The forward current at different temperatures was found to be increased exponentially at low applied voltage $$(V \le 0.4 {\text{V}})$$
 indicating that the conduction mechanism of the diode was controlled by the thermionic emission mechanism. While, at bias voltages higher than 0.5 V, the results obtained show that the carriers conduction was described by the space charge limited current mechanism. The effect of front surface field (FSF) on the photovoltaic parameters of Au/n+ (a-Si:H)/n(SiGe)/p(c-Si) heterojunction solar cell is studied. The experimental results obtained yielded to an improvement of about 50 mV for the open-circuit voltage, 1.1 mA cm−2 for the short-circuit current density, and about 1% for the cell efficiency compared to the conventional cell i.e. without a-Si:H thin layer (FSF).

Electrical transport mechanisms in amorphous silicon/crystalline silicon germanium heterojunction solar cell: impact of passivation layer in conversion efficiency

A 3-D quantum-corrected drift-diffusion (DD) simulation study of three sources of statistical variability, including discrete random dopants (RDs), line-edge roughness (LER), and metal gate workfunction (MGW) was performed for a 14-nm gate length In0.53Ga0.47As FinFET in the subthreshold region using Fermi-Dirac statistics. This paper has been done at both low (0.05 V) and high drain biases (0.6 V). The LER variability is characterized by the root mean square amplitude (Δ) and correlation length (Λ), and the MGW variability by the metal grain size (GS). The RD-induced variation σ VT = 6 mV is similar to that observed in Si SoI FinFETs. The LER-induced threshold voltage variations (σ VT <; 6 mV) are similar to the RD variations when Δ = 1 nm, and smaller than the observed in Si SoI FinFETs (18 mV). For larger A, the LER exhibits σ VT ranging from 11 mV when Λ = 10 nm and Δ = 2 nm to 19 mV when Λ = 20 nm and Δ = 3 nm. The MGW variations are the dominant source of variability in the subthreshold characteristics, the σ VT ranges from 106 mV when GS = 10 nm to 43 mV when GS = 3 nm, which is larger than those observed in equivalent TiN metal-gate Si FinFETs.

Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET

Impact of series and shunt resistances in amorphous silicon thin film solar cells

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrodinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with $\sigma ~{V}_{T}$ values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD ( $\sigma {V}_{T}$ = 8 mV) and minimally influenced by the GER ( $\sigma {V}_{T} \approx 4$ mV). The variability of NS FETs makes them strong candidates to replace FinFETs.

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Simulations of Statistical Variability in n -Type FinFET, Nanowire, and Nanosheet FETs

Simulation data of the performance of amorphous silicon (a-Si:H) thin film solar cells using the software package Sentaurus TCAD (Synopsis Inc) are presented The Sentaurus software is configured with standard theoretical models describing eg the density of states in the mobility gap of a-Si:H, generation/recombination statistics, optical data of a-Si:H thin films etc to calculate illuminated current voltage curves and the respective spectral response for the initial and degraded state of the solar cell For the selected physical properties of the solar cell the simulation data predicts a maximum of the efficiency for an intrinsic a-Si:H layer thickness between 200–250 nm Furthermore, a guideline for the optimization of the p-doped layer thickness and the doping concentration is given

Simulation of the effect of p-layer properties on the electrical behaviour of a-Si:H thin film solar cells

We investigate the impacts of random dopant (RD) and gate workfunction variability on the subthreshold characteristics of a 50-nm-gate-length inversion-mode gate-all-around In0.53Ga0.47As MOSFET using a 3-D finite-element quantum-corrected drift-diffusion device simulator calibrated to experimental data. We have studied threshold voltage, off-current, and subthreshold slope variations. The workfunction variations on the subthreshold characteristics dominate and decrease with the reduction in grain diameter. The simulated grain diameters of 10, 7, and 5 nm exhibit threshold voltage standard deviations of 52, 41, and 27 mV, respectively. These values are larger than those observed in TiN-metal-gate Si FinFETs for a similar gate length. The impact of RD fluctuations is negligible when compared with bulk Si MOSFETs, giving a threshold voltage spread of only 6 mV.

E. Comesana

Papers

Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET

Impact of series and shunt resistances in amorphous silicon thin film solar cells

Simulations of Statistical Variability in n -Type FinFET, Nanowire, and Nanosheet FETs

Simulation of the effect of p-layer properties on the electrical behaviour of a-Si:H thin film solar cells

Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In 0.53 Ga 0.47 As GAA MOSFET