Thin SiO2 oxides implanted by very-low-energy (1 keV) Si ions and subsequently annealed are explored with regards to their potential as active elements of memory devices. Charge storage effects as a function of Si fluence are investigated through capacitance and channel current measurements. Capacitance–voltage and source–drain current versus gate voltage characteristics of devices implanted with a dose of 1×1016 cm−2 or lower exhibit clear hysteresis characteristics at low electric field. The observed fluence dependence of the device electrical properties is interpreted in terms of the implanted oxide structure.

Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si + implantation and annealing

The effect of annealing in diluted oxygen versus inert environment on the structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals fabricated by very low-energy silicon implantation (1 keV) is reported. Annealing in diluted oxygen increases the thickness of the control oxide, improves the integrity of the oxide and narrows the size distribution of the nanocrystals without affecting significantly their mean size (∼2 nm). Strong charge storage effects at low gate voltages and enhanced charge retention times are observed through electrical measurements of metal-oxide-semiconductor capacitors. These results indicate that a combination of low-energy silicon implants and annealing in diluted oxygen allows for the fabrication of improved low-voltage nonvolatile memory devices.

/pdf/effect-of-annealing-environment-on-the-memory-properties-of-3vk0hg95f9.pdf

Effect of annealing environment on the memory properties of thin oxides with embedded Si nanocrystals obtained by low-energy ion-beam synthesis

We investigated the dependence of implantation dose on the charge storage characteristics of large-area n-channel metal–oxide–semiconductor field-effect transistors with 1-keV Si+-implanted gate oxides. Gate bias and time-dependent source–drain current measurements are reported. Devices implanted with 1×1016 cm−2 Si dose exhibit a continuous (trap-like) charge storage process under both static and dynamic conditions. In contrast, for 2×1016 cm−2 implanted devices, electrons are stored in Si nanocrystals in discrete units at low gate voltages, as revealed by a periodic staircase plateau of the source–drain current with a low gate voltage sweep rate, and the step-like decrease of the time-dependent monitoring of the channel current. These observations of room-temperature single-electron storage effects support the pursuit of large-area devices operating on the basis of Coulomb blockade phenomena.

Room-temperature single-electron charging phenomena in large-area nanocrystal memory obtained by low-energy ion beam synthesis

Si-nanocrystal memory devices aiming at low-voltage non-volatile memory applications are explored. The devices consist of a single metal-oxide-semiconductor field-effect-transistor with silicon nanocrystals fabricated through ultra-low-energy (1 keV) Si implantation of the gate oxide (7 nm in thickness) and subsequent thermal annealing. Process issues like boron contamination and parasitic currents that affect the threshold voltage and transfer characteristics of the intended devices are discussed in terms of device structure, process parameter and device simulation. It is shown that these issues can be overcome under appropriate process modifications. Threshold shift of about 2 V are obtained for a 10 ms +9 V/−9 V pulse regime where both electron and hole trapping occur. Neither degradation, nor drift in memory window is detected after 1.5 × 10 6 10 ms +9 V/−9 V cycles. Charge retention measurements reveal that the de-trapping mechanism of stored holes is faster than that of trapped electrons and independent on the temperature. Memory operation with reduced hole trapping, herein demonstrated for a 10 ms +9 V/−7 V regime leading to a 0.3 V 10-year extrapolated memory window at 150 °C, should be preferred for long non-volatile retention of years.

Silicon nanocrystal memory devices obtained by ultra-low-energy ion-beam synthesis

A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.

Method of making volatile memory cell with interface charge traps

Interface traps due to excess Si introduced into the SiSiO 2 system by ion implantation are investigated. Implanted oxides are shown to have interface traps at or slightly above the Si conduction band edge with densities proportional to the density of off-stoichiometric Si at the SiSiO 2 interface. Diluted oxygen annealing is shown to result in physical separation of interface traps and equilibrium substrate electrons, demonstrating that “interface” states are located within a 0.5 nm thick layer of SiO 2 . Possible charge trapping mechanisms are discussed and the effect of these traps on MOS transistor characteristics is described using a sheet charge model.

E.H. Poindexter

Papers

Electronic states at SiSiO2 interface introduced by implantation of Si in thermal SiO2