The energy distribution of electron states at SiC/SiO 2 interfaces produced by oxidation of various (3C, 4H, 6H) SiC polytypes is studied by electrical analysis techniques and internal photoemission spectroscopy. A similar distribution of interface traps over the SiC bandgap is observed for different polytypes indicating a common nature of interfacial defects. Carbon clusters at the SiC/SiO 2 interface and near-interfacial defects in the SiO 2 are proposed to be responsible for the dominant portion of interface traps, while contributions caused by dopant-related defects and dangling bonds at the SiC surface are not observed.

Intrinsic SiC/SiO2 Interface States

The microstructural features of the Si-SiO2 system and the chemical physics of its defects are reviewed and examined. Topics are grouped by scientific commonality, rather than by the usual technological manifestations. The role of atomic and molecular sized entities is emphasized, and the latter are limited to those containing only Si, O, H, or combinations thereof. Most of the reported researches involve x-ray or electron diffraction, Auger or photoelectron spectroscopy, Rutherford backscattering, electron spin resonance, or capacitance-voltage or deep-level transient spectroscopy. Several forms of crystalline and amorphous vitreous silica are considered as a basis for discussion of thin film thermal silica on silicon wafers. Local lattice symmetry, stoichiometry, bond lengths and angles, vacancies and voids, dangling orbital centres, and fixed and migratory hydrogen species are treated extensively. Elements of relevant theory are summarized. Overall, it is hoped to provide a solid data base for future development of general models for essential electronic phenomena in the Si-SiO2 system.

https://iopscience.iop.org/article/10.1088/0034-4885/57/8/002/pdf

The silicon-silicon dioxide system: Its microstructure and imperfections

Total ionizing dose radiation effects on the electrical properties of metal-oxide-semiconductor devices and integrated circuits are complex in nature and have changed much during decades of device evolution. These effects are caused by radiation-induced charge buildup in oxide and interfacial regions. This paper presents an overview of these radiation-induced effects, their dependencies, and the many different approaches to their mitigation.

Radiation effects and hardening of MOS technology: devices and circuits

A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.

Memory using insulator traps

Thin SiO2 oxides implanted by very-low-energy (1 keV) Si ions and subsequently annealed are explored with regards to their potential as active elements of memory devices. Charge storage effects as a function of Si fluence are investigated through capacitance and channel current measurements. Capacitance–voltage and source–drain current versus gate voltage characteristics of devices implanted with a dose of 1×1016 cm−2 or lower exhibit clear hysteresis characteristics at low electric field. The observed fluence dependence of the device electrical properties is interpreted in terms of the implanted oxide structure.

Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si + implantation and annealing

Implantation of Si in does of 1015–1016 cm−2 into dry thermal oxides on silicon wafers produces a three‐state MOS memory device. For both positive‐ and negative‐going traps, gate voltage stress up to ±10 MV/cm−1 generates stable (±) oxide charge near the gate and (∓) charge near the substrate. Electron paramagnetic resonance (EPR) measurement on corona‐field (≤11 MV/cm) stressed oxides reveals E’ centers in regions of positive charge, which may be recycled between the EPR‐visible (+) state and the invisible neutral state. The correspondence of charge and EPR indicates a composite or Feigl‐Fowloer‐Yip E’ center, O3 3/4 Si:...+Si 3/4 O3, arising from nonstoichiometric Si fused into the SiO2 lattice. Upon trapping an electron, the center rebonds to yield O3 3/4 SiSi 3/4 O3. The charging parameters of the E’ center suggest tunneling of an electron from the (0→+) state, and are consistent with the theoretical prediction of the energy level and Franck–Condon relaxation. The three types of E’ centers observed in...

Rechargeable E’ centers in silicon‐implanted SiO2 films

Interface traps due to excess Si introduced into the SiSiO 2 system by ion implantation are investigated. Implanted oxides are shown to have interface traps at or slightly above the Si conduction band edge with densities proportional to the density of off-stoichiometric Si at the SiSiO 2 interface. Diluted oxygen annealing is shown to result in physical separation of interface traps and equilibrium substrate electrons, demonstrating that “interface” states are located within a 0.5 nm thick layer of SiO 2 . Possible charge trapping mechanisms are discussed and the effect of these traps on MOS transistor characteristics is described using a sheet charge model.

P. J. Caplan

Papers

Rechargeable E’ centers in silicon‐implanted SiO2 films

Electronic states at SiSiO2 interface introduced by implantation of Si in thermal SiO2