Journal ArticleDOI
Electronic states at SiSiO2 interface introduced by implantation of Si in thermal SiO2
TLDR
In this article, the authors investigated the effect of interface traps on MOS transistor characteristics using a sheet charge model and showed that the interface states are located within a 0.5 nm thick layer of SiO 2.Abstract:
Interface traps due to excess Si introduced into the SiSiO 2 system by ion implantation are investigated. Implanted oxides are shown to have interface traps at or slightly above the Si conduction band edge with densities proportional to the density of off-stoichiometric Si at the SiSiO 2 interface. Diluted oxygen annealing is shown to result in physical separation of interface traps and equilibrium substrate electrons, demonstrating that “interface” states are located within a 0.5 nm thick layer of SiO 2 . Possible charge trapping mechanisms are discussed and the effect of these traps on MOS transistor characteristics is described using a sheet charge model.read more
Citations
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Journal ArticleDOI
Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si + implantation and annealing
E. Kapetanakis,Pascal Normand,Dimitris Tsoukalas,Konstantinos Beltsios,J. Stoemenos,S. Zhang,J. A. van den Berg +6 more
TL;DR: In this article, the potential of thin SiO2 oxides implanted by very low energy (1 keV) Si ions and subsequently annealed are explored with regards to their potential as active elements of memory devices.
Journal ArticleDOI
Effect of annealing environment on the memory properties of thin oxides with embedded Si nanocrystals obtained by low-energy ion-beam synthesis
Pascal Normand,E. Kapetanakis,Panagiotis Dimitrakis,Dimitris Tsoukalas,Konstantinos Beltsios,Nikolay Cherkashin,Caroline Bonafos,Gérard Benassayag,H. Coffin,Alain Claverie,V. Soncini,Aditya Agarwal,M. Ameen +12 more
TL;DR: In this paper, the effect of annealing in diluted oxygen versus inert environment on the structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals fabricated by very low-energy silicon implantation (1 keV) is reported.
Journal ArticleDOI
Room-temperature single-electron charging phenomena in large-area nanocrystal memory obtained by low-energy ion beam synthesis
TL;DR: In this article, the dependence of implantation dose on the charge storage characteristics of large-area n-channel metaloxide-semiconductor field effect transistors with 1-keV Si+-implanted gate oxides was investigated.
Journal ArticleDOI
Silicon nanocrystal memory devices obtained by ultra-low-energy ion-beam synthesis
Panagiotis Dimitrakis,E. Kapetanakis,Dimitris Tsoukalas,D. Skarlatos,Caroline Bonafos,G Ben Asssayag,Alain Claverie,Michele Perego,Marco Fanciulli,V. Soncini,R Sotgiu,A. Agarwal,M. Ameen,Ch. Sohl,Pascal Normand +14 more
TL;DR: Si-nanocrystal memory devices aiming at lowvoltage non-volatile memory applications are explored in this paper, where a single metaloxide-semiconductor field effect transistor with silicon nanocrystals fabricated through ultra-low energy (1 keV) Si implantation of the gate oxide (7 nm in thickness) and subsequent thermal annealing.
Patent
Method of making volatile memory cell with interface charge traps
TL;DR: In this article, a semiconductor device incorporating electron traps at the interface between a substrate and a gate dielectric layer of an insulated gate field effect transistor is described, such device being capable of retaining charge in the electron traps for a certain time.
References
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Journal ArticleDOI
Gap states in silicon nitride
John Robertson,Martin J. Powell +1 more
TL;DR: In this article, the energy levels of defect states in amorphous silicon nitride have been calculated and the results are used to identify the nature of trap states responsible for charge trapping during transport and the charge storage leading to memory action.
Journal ArticleDOI
Theory of defects in vitreous silicon dioxide
Eoin P. O'Reilly,John Robertson +1 more
TL;DR: In this article, the local electronic structure of the main defects in each model, using the tight-binding and recursion methods, was calculated and compared to that measured by ESR for the paramagnetic centers.
Journal ArticleDOI
Diffusion du silicium dans la silice amorphe
TL;DR: In this paper, the coefficient de diffusion de silicium dans la silice amorphe entre 1110 and 1410°C was measured, in the form of: D(cm 2 s −1 ) = 328 exp (− 579KJ RT ) = 320 exp (− 6eV kT ).