We review some usual laser range finding techniques for in- dustrial applications. After outlining the basic principles of triangulation and time of flight (pulsed, phase-shift and frequency modulated continu- ous wave (FMCW)), we discuss their respective fundamental limitations. Selected examples of traditional and new applications are also briefly presented. © 2001 Society of Photo-Optical Instrumentation Engineers.

Laser ranging: a critical review of usual techniques for distance measurement

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.

0.5-V analog circuit techniques and their application in OTA and filter design

This paper is a review of methods and techniques used for precise measurement of time intervals (TIs) or precise conversion of TIs to digital data. The following methods are described: the counter method and averaging, time stretching, time-to-amplitude conversion followed by analogue-to-digital conversion, the Vernier method, conversion utilizing tapped delay lines, and interpolation methods. Special attention has been paid to converters utilizing integrated delay lines for digital conversion of TIs, including designs with phase-locked loop and delay-locked loop circuits. This review is illustrated by design examples and contains a comprehensive list of references.

https://iopscience.iop.org/article/10.1088/0026-1394/41/1/004/pdf

Review of methods for time interval measurements with picosecond resolution

We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 /spl mu/s with 8.1 ps rms single-shot precision. The resolution of 12.2 ps from a 5-MHz external reference clock is divided by means of only 20 delay elements.

A CMOS time-to-digital converter with better than 10 ps single-shot precision

A time-to-digital converter, TDC, with 780 ps lsb and 10-/spl mu/s input range has been integrated in a 1.2-/spl mu/m CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5/spl plusmn/0.5 V, and the operating temperature range is -40 to +60/spl deg/C. Single-shot accuracy is 3 ns and accuracy after averaging is /spl plusmn/120 ps with input time intervals 5-500 ns. In the total input range of 10 /spl mu/s, the final accuracy after averaging is /spl plusmn/200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm/spl times/2.5 mm. >

A low-power CMOS time-to-digital converter

A time-to-digital converter (TDC) with 32-ps resolution and 2.5-/spl mu/s measurement range has been integrated in a 0.8-/spl mu/m BiCMOS process. The TDC is based on a counter with a 100-MHz clock. Two separate time digitizers improve the time resolution by interpolating within the clock period. These interpolators are based on analog dual-slope conversion. According to test results, the single-shot precision of the TDC is better than 30 ps (/spl sigma/-value) and the nonlinearity is less than /spl plusmn/5 ps when input time intervals range from 10 ns to 2.5 /spl mu/s. The conversion time is /spl les/6.3 /spl mu/s. Temperature drift, excluding the temperature dependence of the oscillator, is below /spl plusmn/40 ps in the temperature range of -40 to 60/spl deg/C. The size of this chip, including pads, is 3.5/spl times/3.4 mm/sup 2/ and its power consumption is 350 mW.

An integrated time-to-digital converter with 30-ps single-shot precision

The design of a CMOS bandgap reference (BGR), for portable applications with medium accuracy, is described and the measurement results of the fabricated chips are presented. The output voltage of the reference is set by resistive subdivision. In order to achieve small area and low power consumption, n-well resistors are used. This design features a reference voltage of 0.750 V with 1/spl sigma/ variation of 10 mV (1.3%) without trimming with a supply voltage range from 1 V to 1.6 V and temperature range of -20/spl deg/C-50/spl deg/C measured from 10 samples. The maximum supply current is 4.5 /spl mu/A and the area of the design is /spl sim/0.13 mm/sup 2/ with a standard 0.35 /spl mu/m double-poly n-well CMOS process.

Design of a 1 V low power CMOS bandgap reference based on resistive subdivision

In this paper, a low-power CMOS operational amplifier for biomedical instrumentation operating with a 1-V supply is described. Large input common-mode range (CMR) is achieved utilizing bulk-driven PMOS-transistors as an input differential pair of the opamp. The opamp was fabricated in a 0.35 /spl mu/m n-well double-poly CMOS process with threshold voltages of 0.5 V and 0.65 V. The open-loop gain (A/sub 0/) of the amplifier is 70 dB, the gain-bandwidth product (GBW) is 190 kHz and the phase margin (PM) is 60/spl deg/ with a 7 pF load. The power consumption of the opamp is 5 /spl mu/W.

A 1-V 5 /spl mu/W CMOS-opamp with bulk-driven input transistors

A 5-MHz, self adjusting CMOS RC-oscillator for portable biomedical applications is presented. The oscillator is capable of operating. with a 1-V power supply and it features low current consumption (20 /spl mu/A @ 1 V) and low sensitivity to supply voltage and temperature variations. The total accuracy of the oscillator is within 5 % with component tolerances of 1 % in external elements R and C. The design was fabricated in a 0.35 /spl mu/m n-well standard digital CMOS process with threshold voltages of 0.5 V and -0.65 V. The design and the operation of the RC-oscillator with measurement results of fabricated chips are presented.

E. Raisanen-Ruotsalainen

Papers

A low-power CMOS time-to-digital converter

An integrated time-to-digital converter with 30-ps single-shot precision

Design of a 1 V low power CMOS bandgap reference based on resistive subdivision

A 1-V 5 /spl mu/W CMOS-opamp with bulk-driven input transistors

A 1-V, self adjusting, 5-MHz CMOS RC-oscillator