In order to model the RF behavior of a device-under-test (DUT), e.g., active and passive devices, dedicated on-wafer test-structures are required. However, parasitic components in the test-structure stemming from the contact pads, the metal interconnections and the silicon substrate, largely influence the RF behavior of the actual DUT. They need to be subtracted from the measurement results if one wants to model the RF behavior of the actual DUT accurately. This subtraction procedure is referred to as de-embedding. In this paper, we propose an improved three-step de-embedding method to subtract the influence of parasitics. The de-embedding method has been applied not only to S-parameter measurement results on MOSFETs but also, for the first time, to large-signal vectorial RF measurements.

Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures

© Cambridge University Press 2007 and Cambridge University Press, 2009.This 2007 book is a comprehensive exposition of FET modeling, and is a must-have resource for seasoned professionals and new graduates in the RF and microwave power amplifier design and modeling community. In it, you will find descriptions of characterization and measurement techniques, analysis methods, and the simulator implementation, model verification and validation procedures that are needed to produce a transistor model that can be used with confidence by the circuit designer. Written by semiconductor industry professionals with many years' device modeling experience in LDMOS and III-V technologies, this was the first book to address the modeling requirements specific to high-power RF transistors. A technology-independent approach is described, addressing thermal effects, scaling issues, nonlinear modeling, and in-package matching networks. These are illustrated using the current market-leading high-power RF technology, LDMOS, as well as with III-V power devices.

Modeling and Characterization of RF and Microwave Power FETs

This paper focuses on the determination and analysis of an accurate small-signal equivalent circuit for gallium-nitride high electron-mobility transistors under different bias conditions. Our experimental results show that a channel capacitance has to be added to the conventional forward "cold" model for modeling the device-under-test. The validity of the proposed extraction procedure has been verified by the very good agreement between simulated and measured scattering parameters up to 50 GHz

Accurate Multibias Equivalent-Circuit Extraction for GaN HEMTs

Integrated solenoid inductors with magnetic core were fabricated and analyzed. An inductance above 70 nH was achieved while keeping the coil resistance below 1 Omega and the device area below 1 mm2 using a solenoid design with a single magnetic layer. The inductance of the magnetic inductor was more than 30 times that of the air core inductor of the identical geometry, and the quality factor of the magnetic inductor was >5. Novel inductor designs and the scalability were also examined, and an inductance density higher than 200 nH/mm2 was obtained. The measured device properties and engineering tradeoffs were well explained by analytical models we developed.

Fabrication and Analysis of High-Performance Integrated Solenoid Inductor With Magnetic Core

The impedance errors remaining after conventional de-embedding for a high-speed transistor and a single-loop inductor test structure are investigated. A new de-embedding strategy using a physics-based lumped-element model for the test-structure parasitics calibrated on the frequency-dependent "open" and "short" dummy impedances is described, which reduces the experimental uncertainty on the de-embedded figures of merit. Using this new "calibrated lumped-element" de-embedding technique, we have been able to increase the "worst-case" values for the quality factor Q of a 0.6-nH 10-GHz single-loop inductor from 15 to 20 and for the f/sub max/ of a high-speed SiGe bipolar transistor from 80 to 110 GHz. The de-embedding technique presented here is of great importance to develop confidence in on-wafer S-parameter measurements taken at ever increasing microwave frequencies.

A calibrated lumped-element de-embedding technique for on-wafer RF characterization of high-quality inductors and high-speed transistors

AlGaN/GaN HEMTs have a high potential for high-power applications at microwave frequencies. We developed a behavioural model corresponding to the operation condition as how this device will be used in power amplifiers, i.e., at a high output load. The model is based on time-domain large-signal measurements, and the representation format is an artificial neural network (ANN). AlGaN/GaN devices on sapphire are known to be temperature sensitive. Therefore, we also consider the incorporation of the self-heating effect in the behavioural model description.

ANN model for AlGaN/GaN HEMTs constructed from near-optimal-load large-signal measurements

Silicon technology development requires a continuous effort to improve performance and reduce costs. Besides scaling down di­ mensions, significant improvements can be achieved by fine tuning critical technologi­ cal parameters, like gate oxide thickness, well doping, junction profiles and thermal

http://ieeexplore.ieee.org/iel5/10061/32274/01505581.pdf

E. Vandamme

Papers

Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures

ANN model for AlGaN/GaN HEMTs constructed from near-optimal-load large-signal measurements

Optimisation of Critical Parameters in a Low Cost, High Performance Deep Submicron CMOS Technology

Large-signal network analyzer measurements and their use in device modelling

Reliable extraction of RF figures-of-merit for MOSFETs