In very small electronic devices the alternate capture and emission of carriers at an individual defect site generates discrete switching in the device resistance—referred to as a random telegraph signal (RTS) The study of RTSs has provided a powerful means of investigating the capture and emission kinetics of single defects, has demonstrated the defect origins of low-frequency (1/ƒ) noise in these devices, and has provided new insight into the nature of defects at the Si/SiO2 interface

Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/ƒ) noise

We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss the effects of varying parameters (hydrogen, deuterium, nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gate length) on NBTI. We conclude with the present understanding of NBTI and its minimization.

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

This review describes recent groundbreaking results in Si, Si/SiGe, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the physical understanding of quantum effects in silicon. Recent critical steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.

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Silicon quantum electronics

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.

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Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties

Interface states and electron spin resonance centers have been observed and compared in thermally oxidized (111) and (100) silicon wafers subjected to various processing treatments. The ESR Pb signal, previously assigned to interface ⋅Si≡Si3 defects on (111) wafers, was found to have two components on (100): an ⋅Si≡Si3 center oriented in accord with (100) face structure, and an unidentified center consistent with ⋅Si≡Si2O. The quantitative proportionality of Pb spin concentration to midgap interface trap density Dit is maintained on (100), and both are lower by a factor of about 3 compared to (111). This correlation persists over the range of oxidation temperatures 800–1200°C, for both n‐ and p‐doped silicon, cooled by fast pull in oxygen, and cooled or annealed in nitrogen or argon. The correlation is independent of doping level. In samples with different oxide thickness, neither Pb nor Dit varied significantly over the range 100–2000 A, but Pb was smaller at 50 A. In general, ESR is judged to offer prom...

Interface states and electron spin resonance centers in thermally oxidized (111) and (100) silicon wafers

The ESR Pb center has been observed in thermally oxidized single‐crystal silicon wafers, and compared with oxide fixed charge Qss and oxidation‐induced interface states Nst. The Pb center is found to be located near the interface on (111) wafers. Its g anisotropy is very similar to that of known bulk silicon defects having SiIII bonded to three other Si atoms; the Pb unpaired electron orbital, however, is exclusively oriented normal to the (111) surface. The Pb center cannot be identified with any other known defect in Si or SiO2; in particular, it is totally unlike the common E′ center of SiO2. In contrast to Qss, both Pb and Nst were found to be greatly reduced by steam oxidation and hydrogen annealing. Both Pb and Nst may be regenerated by subsequent N2 anneals at 500 °C. In a graded series of samples, Pb and Nst are found to be proportional and nearly equal in concentration. This possible confirmation of SiIII at the interface, and correlation with Nst, support the theoretical indication of an SiIII b...

ESR centers, interface states, and oxide fixed charge in thermally oxidized silicon wafers

Energy distribution of Pb centers (⋅Si≡Si3) and electronic traps (Dit) at the Si/SiO2 interface in metal‐oxide‐silicon (MOS) structures was examined by electric‐field‐controlled electron paramagnetic resonance (EPR) and capacitance‐voltage (C‐V) analysis on the same samples Chips of (111)‐oriented silicon were dry‐oxidized for maximum Pb and trap density, and metallized with a large MOS capacitor for EPR and adjacent small dots for C‐V measurements Analysis of C‐V data shows two Dit peaks of amplitude 2×1013 eV−1 cm−2 at Ev+026 eV and Ev+084 eV The EPR spin density reflects addition or subtraction of an electron from the singly occupied paramagnetic state and shows transitions of amplitude 15×1013 eV−1 cm−2 at Ev+031 eV and Ev+080 eV This correlation of electrical and EPR responses and their identical chemical and physical behavior are strong evidence that ⋅Si≡Si3 is a major source of interface electronic traps in the 015–095 eV region of the Si band gap in unpassivated material

Electronic traps and Pb centers at the Si/SiO2 interface: Band‐gap energy distribution

The band‐gap energy distribution of Pb centers on oxidized (100) Si wafers has been determined and compared with interface electrical trap density Dit. Two different Pb centers are observed on (100) Si: Pb0, which has the structure ⋅Si≡Si3, and is essentially identical to the sole Pb center observed on (111) Si; and Pb1, of presently uncertain identity, but clearly different in nature from Pb0. By electric field‐controlled electron paramagnetic resonance (EPR) and capacitance‐voltage (C‐V) measurements, it is found that Pb0 has its (0↔1) electron transition at Ev+0.3 eV and its (1↔2) transition at Ev+0.85 eV. Similarly, Pb1 has its (0↔1) transition at Ev+0.45 eV and its (1↔2) transition at Ev+0.8 eV. The Pb band‐gap density correlates qualitatively and quantitatively with the electrical trap density Dit from C‐V analysis; nonbonded Pb orbitals are found to be the source of about 50% of the characteristic traps in dry‐oxidized, unannealed (100) Si wafers.

Edward H. Poindexter

Papers

Interface states and electron spin resonance centers in thermally oxidized (111) and (100) silicon wafers

ESR centers, interface states, and oxide fixed charge in thermally oxidized silicon wafers

Electronic traps and Pb centers at the Si/SiO2 interface: Band‐gap energy distribution

Interface traps and Pb centers in oxidized (100) silicon wafers

Characterization of Si/SiO2 interface defects by electron spin resonance