E
Eiji Takeda
Researcher at Hitachi
Publications - 64
Citations - 2567
Eiji Takeda is an academic researcher from Hitachi. The author has contributed to research in topics: Field-effect transistor & MOSFET. The author has an hindex of 28, co-authored 63 publications receiving 2512 citations.
Papers
More filters
Proceedings ArticleDOI
A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET
TL;DR: A fully depleted lean channel transistor (DELTA) with a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported in this paper.
Journal ArticleDOI
An experimental 1.5-V 64-Mb DRAM
Y. Nakagome,Tanaka Haruhiko,Kan Takeuchi,E. Kume,Y. Watanabe,Toru Kaga,Yoshifumi Kawamoto,Fumio Murai,R. Izawa,Digh Hisamoto,T. Kisu,Takashi Nishida,Eiji Takeda,K. Itoh +13 more
TL;DR: In this paper, an accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed to reduce data transmission delay.
Journal ArticleDOI
A new aspect of mechanical stress effects in scaled MOS devices
TL;DR: In this paper, a stress analysis program, SIMUS (stress analysis program for multilayer structure) 2D/F, which can analyze the stress state of thin multi-layer structures such as LSI devices throughout their manufacturing process, was used.
Journal ArticleDOI
Impact of the vertical SOI 'DELTA' structure on planar device technology
TL;DR: In this paper, a fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented.
Journal ArticleDOI
A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET
TL;DR: In this article, a fully depleted lean-channel transistor (DELTA) with a gate with a vertical ultrathin SOI structure is reported, which provides high crystalline quality, as good as that of conventional bulk single-crystal devices.